Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package

• US 20070138628A1
• Filed: 12/15/2005
• Published: 06/21/2007
• Est. Priority Date: 12/15/2005
• Status: Abandoned Application

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Lam, Ken
• Application Number:
  US11/304,084
• Publication Number:
  US 20070138628A1
• Time in Patent Office: Days
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An apparatus and method for incorporating discrete passive components into an integrated circuit package. A first surface of a substrate is coated with a material to mechanically protect the first surface. A first metal layer and then an insulating layer are formed on a second surface of the substrate. Selected areas are removed from the insulating and a second metal layer is formed over the insulating layer and the exposed metal layer. Selected areas of the second metal layer are removed to form a plurality of structures, including at least one of a wirebonding pad, a solder-bonding pad, a device interconnect circuit, or an attach pad to which an electronic component may be attached. An electronic component may be attached to at least one of the structures. The resulting integrated circuit die may be incorporated into an electronic package.

Claims

1. A method of fabrication comprising:

a) providing a substrate with a first surface having a passivation layer; and

b) building a plurality of structures on a second surface of the substrate, the plurality of structures including at least one structure to which an electronic component may be attached, the plurality of structures including at least one of the following;

i) a wirebonding pad;

ii) a solder-bonding pad;

iii) a device interconnect circuit;

or

iv) an attach pad to which an electronic component can be attached.

2. The method of claim 1 wherein building the plurality of structures includes forming a metal layer on the second surface of the substrate.

3. The method of claim 2 wherein building the plurality of structures includes forming an insulating layer on the metal layer.

4. The method of claim 3 wherein building the plurality of structures includes removing selected areas of the insulating layer, thereby exposing portions of the first metal layer.

5. The method of claim 4 wherein building the plurality of structures includes forming a second metal layer over the insulating layer and the exposed portions of the first metal layer.

6. The method of claim 5 wherein building the plurality of structures includes removing selected areas of the second metal layer to form the plurality of structures.

7. The method of claim 1 further comprising attaching the substrate to an electronic package.

8. The method of claim 7 wherein the package is a multi-chip module package.

9. The method of claim 1 further comprising coating the first surface with a material to mechanically protect the first surface.

10. The method of claim 1 further comprising attaching the electronic component to the attach pad.

11. The method of claim 10 wherein the electronic component is either an active or passive component.

12. The method of claim 1 wherein the substrate is a semiconductor substrate.

13. The method of claim 1 wherein the second surface is silicon or gallium arsenide.

14. An electronic package comprising:

a) a substrate;

b) an integrated circuit die coupled to a first surface of the substrate, a first surface of the integrated circuit die having a means for coupling to the first surface of the substrate, at least one first electronic component attached to the first surface of the integrated circuit die, at least one structure attached to a second surface of the integrated circuit die, the at least one structure configured to be coupled to a second electronic component.

15. The electronic package of claim 14 wherein the at least one structure attached to the second surface includes at least one of the following:

a) a wirebonding pad;

b) a solder-bonding pad;

c) a device interconnect circuit;

or

d) an attach pad to which the second electronic component may be coupled.

16. The electronic package of claim 15 further comprising the second electronic component attached to the at least one structure.

17. The electronic package of claim 16 further comprising the second electronic component coupled to the substrate.

18. The electronic package of claim 17 wherein the second electronic component is coupled to the substrate by a wirebond.

19. The electronic package of claim 16 wherein the second electronic component is either an active or passive component.

20. The electronic package of claim 14 wherein the electronic package is a multi-chip module package.

21. The electronic package of claim 14 wherein the substrate is a printed circuit board.

23. The electronic package of claim 14 wherein the at least one structure attached to the second surface includes at least one of the following:

a) a wirebonding pad;

b) a solder-bonding pad;

c) a device interconnect circuit;

or

d) an attach pad to which the second electronic component may be coupled.

24. The electronic package of claim 23 further comprising a second electronic component attached to the at least one structure.

25. The electronic package of claim 23 wherein the second electronic component is either an active or passive component.

22. An electronic package comprising:

a) a substrate;

b) a flip chip attached to a first surface of the substrate, a first surface of the flip chip having a means for attachment to the first surface of the substrate, at least one first electronic component attached to the first surface of the flip chip, at least one structure attached to a second surface of the flip chip, the at least one structure configured to be coupled to a second electronic component.

26. The electronic package of claim 22 wherein the electronic package is a multi-chip module package.

27. The electronic package of claim 22 wherein the substrate is a printed circuit board.

28. A semiconductor device comprising:

a) a first substrate having a first surface and a second surface;

b) a passivation layer on the first surface of the first substrate; and

c) at least one structure attached to the second surface of the first substrate, the at least one structure configured to be coupled to an electronic component.

29. The semiconductor device of claim 28 wherein the at least one structure includes at least one of the following:

a) a wirebonding pad;

b) a solder-bonding pad;

c) a device interconnect circuit;

or

d) an attach pad to which the electronic component may be attached.

30. The semiconductor device of claim 28 further comprising a means for attachment to a second substrate, the means for attachment coupled to the first surface of first substrate.

31. The semiconductor device of claim 30 wherein the second substrate is attached to an electronic package.

32. The semiconductor device of claim 30 further comprising at least one electronic component attached to the at least one structure.

33. The semiconductor device of claim 28 wherein the first substrate is a semiconductor substrate.

34. The semiconductor device of claim 28 wherein the semiconductor substrate is silicon or gallium arsenside.

35. The semiconductor device of claim 32 wherein the at least one electronic component is an active or passive component.

36. The semiconductor device of claim 30 wherein the second substrate is a semiconductor substrate.

37. A method of integrated circuit device packaging comprising:

a) providing a substrate;

b) coupling a first surface of an integrated circuit die to the substrate, the first surface coupled to at least one electronic component; and

c) attaching at least one electronic component to at least one structure on a second surface of the integrated circuit die.

38. The method of claim 37 wherein the first surface of the integrated circuit die is coupled to the substrate by solder balls.

39. The method of claim 37 wherein the first surface of the integrated circuit die is coupled to the substrate by wirebond.

40. The method of claim 37 further comprising coupling the at least one electronic component to the substrate.

41. The method of claim 37 wherein the at least one electronic component is coupled to the substrate by a wirebond.

42. The method of claim 37 wherein the electronic component is either an active or passive component.

43. The method of claim 37 wherein the substrate is a printed circuit board.