Signa-delta modulation with offset

• US 20070139239A1
• Filed: 07/19/2006
• Published: 06/21/2007
• Est. Priority Date: 07/19/2006
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Keehr, Edward Arthur
• Granted Patent: US 7,456,766 B2
• Time in Patent Office: Days
• US Class Current: 341/143
• CPC Class Codes: H03M 3/50 Digital/analogue converters using delta-sigma modulation as an intermediate step digital delta-sigma modulators per se H03M7/3004
• CPC Class Codes: H03M 7/3006 Compensating for, or preventing of, undesired influence of physical parameters

Abstract

Techniques for performing ΣΔ modulation with offset in order to reduce out-of-band quantization noise are described. In an exemplary oversampling DAC that implements ΣΔ modulation with offset, an interpolation filter performs upsampling and interpolation filtering on data samples to generate input samples. A summer adds an offset to the input samples to generate intermediate samples. The offset alters the characteristics of the quantization noise from a ΣΔ modulator and may be selected to obtain the desired quantization noise characteristics, to retain as much dynamic range as possible, and to simplify the removal of the offset. The ΣΔ modulator performs upsampling and noise shaping on the intermediate samples and provides output samples. An offset removal unit removes at least a portion of the offset from the output samples in the digital or analog domain. A DAC converts the output samples to analog.

Claims

1. An apparatus comprising:

a summer configured to add an offset to input samples to generate intermediate samples; and

a sigma-delta modulator configured to perform noise shaping on the intermediate samples and provide output samples.

2. The apparatus of claim 1, further comprising:

an offset removal unit configured to remove at least a portion of the offset from the output samples.

3. The apparatus of claim 1, further comprising:

an offset removal unit configured to digitally remove at least a portion of the offset from the output samples.

4. The apparatus of claim 1, wherein each output sample comprises multiple bits.

5. The apparatus of claim 4, further comprising:

an offset removal unit configured to invert each of the multiple bits of each output sample to remove at least a portion of the offset.

6. The apparatus of claim 1, further comprising:

an interpolation filter configured to perform upsampling and interpolation filtering on data samples and provide the input samples.

7. The apparatus of claim 1, further comprising:

a digital-to-analog converter (DAC) comprising a plurality of DAC elements and configured to convert the output samples to analog; and

a dynamic element matching (DEM) unit configured to select different ones of the plurality of DAC elements based on the output samples.

8. The apparatus of claim 7, wherein the DAC is a switch-capacitor DAC, and wherein the plurality of DAC elements comprise a plurality of switchable capacitors.

9. The apparatus of claim 7, wherein the DEM unit is configured to select the plurality of DAC elements based on a data weighted averaging (DWA) scheme.

10. The apparatus of claim 7, further comprising:

a lowpass filter configured to filter an analog output from the DAC.

11. The apparatus of claim 10, wherein the lowpass filter is a switch-capacitor filter.

12. The apparatus of claim 1, wherein the offset added to the input samples results in the output samples having an offset of approximately −

1.

13. The apparatus of claim 1, wherein the input samples have 16 bits of resolution, and wherein the offset is −

4929.

14. The apparatus of claim 1, wherein the summer and the sigma-delta modulator are part of an oversampling DAC.

15. The apparatus of claim 1, wherein the input samples are for an audio signal.

16. An integrated circuit comprising:

a summer configured to add an offset to input samples to generate intermediate samples; and

a sigma-delta modulator configured to perform noise shaping on the intermediate samples and provide output samples.

17. The integrated circuit of claim 16, further comprising:

an offset removal unit configured to remove at least a portion of the offset from the output samples.

18. The integrated circuit of claim 16, further comprising:

an interpolation filter configured to perform upsampling and interpolation filtering on data samples and provide the input samples.

19. A method comprising:

adding an offset to input samples to generate intermediate samples; and

performing noise shaping on the intermediate samples to generate output samples.

20. The method of claim 19, further comprising:

removing at least a portion of the offset from the output samples.

21. The method of claim 19, further comprising:

performing upsampling and interpolation filtering on data samples to generate the input samples.

22. The method of claim 19, further comprising:

converting the output samples to analog using a plurality of digital-to-analog converter (DAC) elements; and

selecting different ones of the plurality of DAC elements based on the output samples.

23. An apparatus comprising:

means for adding an offset to input samples to generate intermediate samples; and

means for performing noise shaping on the intermediate samples to generate output samples.

24. The apparatus of claim 23, further comprising:

means for removing at least a portion of the offset from the output samples.

25. The apparatus of claim 23, further comprising:

means for performing upsampling and interpolation filtering on data samples to generate the input samples.

26. The apparatus of claim 23, further comprising:

means for converting the output samples to analog using a plurality of digital-to-analog converter (DAC) elements; and

means for selecting different ones of the plurality of DAC elements based on the output samples.