ANALOG TO DIGITAL CONVERTER CIRCUIT WITH OFFSET REDUCTION AND IMAGE SENSOR USING THE SAME
First Claim
1. An image sensor circuit comprising:
- an array of pixels comprised of rows and columns of pixel circuits;
a row driver for supplying respective control signals to rows of said pixel circuits; and
respective analog to digital converters connected to receive signals produced by columns of said pixel circuits;
wherein each of said analog to digital converters comprises;
a first input node for receiving a reference value;
a second input node for receiving a pixel signal value;
an autozeroing amplifier section having respective inputs coupled to the first and second input nodes and being capable of performing an offset reduction operation to compensate for offset between its inputs;
a comparator section having respective inputs coupled to respective outputs of the autozeroing amplifier section;
said comparator section capable of performing an offset reduction operation to compensate for offset between its inputs and capable of performing a decision operation using positive feedback to decide which of its inputs is being provided with a higher input voltage;
a group of binary scaled capacitors having respective first nodes coupled to the second input node; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the comparator section, wherein signals within an analog to digital converter are amplified by the autozeroing amplifier section before being supplied to the comparator section to reduce the effect of comparator section offset on comparator section decisions.
1 Assignment
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Accused Products
Abstract
An image sensor may be improved by using ADCs that compensate for the effect of comparator input offset on comparator decisions. Offset compensation may be implemented in an ADC by using an amplifier section between the input of the ADC and a comparator section of the ADC to amplify the signals supplied to the comparator inputs and thereby reduce the effect of comparator offset on the comparator decision. The comparator section may be an autozeroing comparator section that is capable of performing an offset reduction operation to store offset compensation values at capacitors provided at its inputs. The amplifier section may be an autozeroing amplifier section having one or more amplifier stages that are capable of performing an offset reduction operation to store offset compensation values at capacitors provided at their inputs. Offset compensation may also be implemented using an autozeroing comparator section without a preceding amplifier section. Related methods of operation cause the circuits to perform the offset reduction operations.
39 Citations
58 Claims
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1. An image sensor circuit comprising:
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an array of pixels comprised of rows and columns of pixel circuits;
a row driver for supplying respective control signals to rows of said pixel circuits; and
respective analog to digital converters connected to receive signals produced by columns of said pixel circuits;
wherein each of said analog to digital converters comprises;
a first input node for receiving a reference value;
a second input node for receiving a pixel signal value;
an autozeroing amplifier section having respective inputs coupled to the first and second input nodes and being capable of performing an offset reduction operation to compensate for offset between its inputs;
a comparator section having respective inputs coupled to respective outputs of the autozeroing amplifier section;
said comparator section capable of performing an offset reduction operation to compensate for offset between its inputs and capable of performing a decision operation using positive feedback to decide which of its inputs is being provided with a higher input voltage;
a group of binary scaled capacitors having respective first nodes coupled to the second input node; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the comparator section, wherein signals within an analog to digital converter are amplified by the autozeroing amplifier section before being supplied to the comparator section to reduce the effect of comparator section offset on comparator section decisions. - View Dependent Claims (2, 3, 4, 5, 7, 8, 9, 10, 16, 51, 52)
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6. An image sensor circuit comprising:
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an array of pixels comprised of rows and columns of pixel circuits;
a row driver for supplying respective control signals to rows of said pixel circuits; and
respective analog to digital converters connected to receive signals produced by columns of said pixel circuits;
wherein each of said analog to digital converters comprises;
a first input node for receiving a reference value;
a second input node for receiving a pixel signal value;
an autozeroing amplifier section having respective inputs coupled to the first and second input nodes and being capable of performing an offset reduction operation to compensate for offset between its inputs;
a comparator section having respective inputs coupled to respective outputs of the autozeroing amplifier section;
a group of binary scaled capacitors having respective first nodes coupled to the second input node; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the comparator section;
wherein signals within an analog to digital converter are amplified by the autozeroing amplifier section before being supplied to the comparator section to reduce the effect of comparator section offset on comparator section decisions;
wherein the autozeroing amplifier section comprises at least one autozeroing amplifier stage;
wherein each of said at least one autozeroing amplifier stages comprises first and second input transistors for receiving respective input signals at their gates, and first and second reset transistors coupled between the respective gates of the first and second input transistors and respective first and second outputs of the autozeroing amplifier stage; and
wherein each of said first and second input transistors is connected in series with a respective second transistor to form a cascode circuit.
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11. An image sensor circuit comprising:
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an array of pixels comprised of rows and columns of pixel circuits;
a row driver for supplying respective control signals to rows of said pixel circuits; and
respective analog to digital converters connected to receive signals produced by columns of said pixel circuits;
wherein each of said analog to digital converters comprises;
a first input node for receiving a pixel reset value;
a second input node for receiving a pixel signal value;
an autozeroing comparator section having respective inputs coupled to the first input node and second input node and being capable of performing an offset reduction operation to compensate for offset between its inputs;
a group of binary scaled capacitors having respective first nodes coupled to the second input node; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the autozeroing comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the autozeroing comparator section;
wherein the autozeroing comparator section comprises;
a first input transistor for receiving a first input signal at its gate, and a second input transistor for receiving a second input signal at its gate;
a first reset transistor coupled between a gate of the first input transistor and a first output of the autozeroing comparator section, and a second reset transistor coupled between a gate of the second input transistor and a second output of the autozeroing comparator section;
a first load transistor coupled between the first output of the autozeroing comparator section and a voltage source node, and a second load transistor coupled between the second output of the autozeroing comparator section and the voltage source node;
a first autozero enable transistor coupled between a gate of the first load transistor and the first output of the comparator, and a second autozero enable transistor coupled between a gate of the second load transistor and the second output of the comparator;
a first comparator enable transistor coupled between the first output of the comparator and the gate of the second load transistor, and a second comparator enable transistor coupled between the second output of the comparator and the gate of the first load transistor;
a first preset transistor coupled between the first output of the comparator and the voltage source node, and a second preset transistor coupled between the second output of the comparator and the voltage source node; and
a first current enable transistor coupled in a path between the first input transistor and a ground node, and a second current enable transistor coupled in a path between the second input transistor and a ground node. - View Dependent Claims (12, 13, 15, 17)
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14. (canceled)
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18. An image sensor circuit comprising:
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an array of pixels comprised of rows and columns of pixel circuits;
a row driver for supplying respective control signals to rows of said pixel circuits; and
respective analog to digital converters connected to receive signals produced by columns of said pixel circuits;
wherein each of said analog to digital converters comprises;
a first input node for receiving a reference value;
a second input node for receiving a pixel signal value;
an amplifier section having respective inputs coupled to the first and second input nodes;
an autozeroing comparator section having respective inputs coupled to respective outputs of the amplifier section, autozeroing comparator section capable of performing an offset reduction operation to compensate for offset between its inputs and capable of performing a decision operation using positive feedback to decide which of its inputs is being provided with a higher input voltage;
a group of binary scaled capacitors having respective first nodes coupled to the second input node; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the autozeroing comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the comparator section, wherein signals within an analog to digital converter are amplified by the amplifier section before being supplied to the autozeroing comparator section to reduce the effect of comparator section offset on comparator section decisions. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 27, 32, 33, 34, 53, 54)
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26. An image sensor circuit comprising:
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an array of pixels comprised of rows and columns of pixel circuits;
a row driver for supplying respective control signals to rows of said pixel circuits; and
respective analog to digital converters connected to receive signals produced by columns of said pixel circuits;
wherein each of said analog to digital converters comprises;
a first input node for receiving a reference value;
a second input node for receiving a pixel signal value;
an amplifier section having respective inputs coupled to the first and second input nodes;
an autozeroing comparator section having respective inputs coupled to respective outputs of the amplifier section and being capable of performing an offset reduction operation to compensate for offset between its inputs;
a group of binary scaled capacitors having respective first nodes coupled to the second input node; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the autozeroing comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the comparator section;
wherein signals within an analog to digital converter are amplified by the amplifier section before being supplied to the autozeroing comparator section to reduce the effect of comparator section offset on comparator section decisions;
wherein the amplifier section is an autozeroing amplifier section capable of performing an offset reduction operation to compensate for offset between its inputs;
wherein the autozeroing amplifier section comprises at least one autozeroing amplifier stage;
wherein each of said at least one autozeroing amplifier stages comprises first and second input transistors for receiving respective input signals at their gates, and first and second reset transistors coupled between the respective gates of the first and second input transistors and the respective first and second outputs of the autozeroing amplifier stage; and
wherein each of said first and second input transistors is connected in series with a respective second transistor to form a cascode circuit.
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28. An image sensor circuit comprising:
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an array of pixels comprised of rows and columns of pixel circuits;
a row driver for supplying respective control signals to rows of said pixel circuits; and
respective analog to digital converters connected to receive signals produced by columns of said pixel circuits;
wherein each of said analog to digital converters comprises;
a first input node for receiving a reference value;
a second input node for receiving a pixel signal value;
an amplifier section having respective inputs coupled to the first and second input nodes;
an autozeroing comparator section having respective inputs coupled to respective outputs of the amplifier section and being capable of performing an offset reduction operation to compensate for offset between its inputs;
a group of binary scaled capacitors having respective first nodes coupled to the second input node; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the autozeroing comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the comparator section;
wherein signals within an analog to digital converter are amplified by the amplifier section before being supplied to the autozeroing comparator section to reduce the effect of comparator section offset on comparator section decisions; and
wherein the autozeroing comparator section comprises;
a first input transistor for receiving a first input signal at its gate, and a second input transistor for receiving a second input signal at its gate;
a first reset transistor coupled between a gate of the first input transistor and a first output of the autozeroing comparator section, and a second reset transistor coupled between a gate of the second input transistor and a second output of the autozeroing comparator section;
a first load transistor coupled between the first output of the comparator and a voltage source node, and a second load transistor coupled between the second output of the comparator and the voltage source node;
a first autozero enable transistor coupled between a gate of the first load transistor and the first output of the comparator, and a second autozero enable transistor coupled between a gate of the second load transistor and the second output of the comparator;
a first comparator enable transistor coupled between the first output of the comparator and the gate of the second load transistor, and a second comparator enable transistor coupled between the second output of the comparator and the gate of the first load transistor;
a first preset transistor coupled between the first output of the comparator and the voltage source node, and a second preset transistor coupled between the second output of the comparator and the voltage source node; and
a first current enable transistor coupled in a path between the first input transistor and a ground node, and a second current enable transistor coupled in a path between the second input transistor and a ground node. - View Dependent Claims (29, 30, 31)
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35. An analog to digital conversion circuit comprising:
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a first input node for receiving a first value;
a second input node for receiving a second value;
an amplifier section having respective inputs coupled to the first and second input nodes;
an autozeroing comparator section having respective inputs coupled to respective outputs of the amplifier section, said autozeroing comparator section all capable of performing an offset reduction operation to compensate for offset between its inputs and capable of performing a decision operation using positive feedback to decide which of its inputs is being provided with a higher input voltage;
a group of binary scaled capacitors having respective first nodes coupled to the second input node; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the autozeroing comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the comparator section, wherein signals within an analog to digital converter are amplified by the amplifier section before being supplied to the autozeroing comparator section to reduce the effect of comparator section offset on comparator section decisions. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 44, 55, 56)
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43. An analog to digital conversion circuit comprising:
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a first input node for receiving a first value;
a second input node for receiving a second value;
an amplifier section having respective inputs coupled to the first and second input nodes;
an autozeroing comparator section having respective inputs coupled to respective outputs of the amplifier section and being capable of performing an offset reduction operation to compensate for offset between its inputs;
a group of binary scaled capacitors having respective first nodes coupled to the second input node; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the autozeroing comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the comparator section;
wherein signals within an analog to digital converter are amplified by the amplifier section before being supplied to the autozeroing comparator section to reduce the effect of comparator section offset on comparator section decisions;
wherein the amplifier section is an autozeroing amplifier section capable of performing an offset reduction operation to compensate for offset between its inputs;
wherein the autozeroing amplifier section comprises at least one autozeroing amplifier stage;
wherein each of said at least one autozeroing amplifier stages comprises first and second input transistors for receiving respective input signals at their gates, and first and second reset transistors coupled between the respective gates of the first and second input transistors and the respective first and second outputs of the autozeroing amplifier stage; and
wherein each of said first and second input transistors is connected in series with a respective second transistor to forms a cascode circuit.
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45. An analog to digital conversion circuit comprising:
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a first input node for receiving a first value;
a second input node for receiving a second value;
an amplifier section having respective inputs coupled to the first and second input nodes;
an autozeroing comparator section having respective inputs coupled to respective outputs of the amplifier section and being capable of performing an offset reduction operation to compensate for offset between its inputs;
a group of binary scaled capacitors having respective first nodes coupled to the second input node; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the autozeroing comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the comparator section;
wherein signals within an analog to digital converter are amplified by the amplifier section before being supplied to the autozeroing comparator section to reduce the effect of comparator section offset on comparator section decisions; and
wherein the autozeroing comparator section comprises;
a first input transistor for receiving a first input signal at its gate, and a second input transistor for receiving a second input signal at its gate;
a first reset transistor coupled between a gate of the first input transistor and a first output of the autozeroing comparator section, and a second reset transistor coupled between a gate of the second input transistor and a second output of the autozeroing comparator section;
a first load transistor coupled between the first output of the comparator and a voltage source node, and a second load transistor coupled between the second output of the comparator and the voltage source node;
a first autozero enable transistor coupled between a gate of the first load transistor and the first output of the comparator, and a second autozero enable transistor coupled between a gate of the second load transistor and the second output of the comparator;
a first comparator enable transistor coupled between the first output of the comparator and the gate of the second load transistor, and a second comparator enable transistor coupled between the second output of the comparator and the gate of the first load transistor;
a first preset transistor coupled between the first output of the comparator and the voltage source node, and a second preset transistor coupled between the second output of the comparator and the voltage source node; and
a first current enable transistor coupled in a path between the first input transistor and a ground node, and a second current enable transistor coupled in a path between the second input transistor and a ground node. - View Dependent Claims (46, 47, 48)
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49. A method in an analog to digital converter comprising, connecting respective inputs of a comparator of the analog to digital converter to corresponding outputs of the analog to digital converter to store offset compensation values in respective capacitors coupled to the respective inputs of the comparator;
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contemporaneously with connecting the inputs of the comparator to the corresponding outputs of the comparator, connecting respective inputs of an amplifier of the analog to digital converter to corresponding outputs of the amplifier;
disconnecting the inputs of the amplifier from the corresponding outputs of the amplifier;
disconnecting the inputs of the comparator from the corresponding outputs of the comparator after disconnecting the inputs of the amplifier from the corresponding outputs of the amplifier; and
providing a series of one or more signals at the respective inputs of the comparator to produce a series of output decisions by the comparator, wherein said series of one or more signals provided at the respective inputs of the comparator are provided through said amplifier.
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50. (canceled)
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57. A circuit, comprising:
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a comparator having a plurality of inputs;
wherein the comparator is capable of performing an offset reduction operation to compensate for offset between the plurality of inputs; and
wherein the comparator is capable of performing a decision operation using positive feedback to decide which of the plurality of inputs is being provided with a highest input voltage. - View Dependent Claims (58)
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Specification