Method for reducing memory consumption when carrying out edge enhancement in multiple beam pixel apparatus
First Claim
1. A method for reducing memory consumption when carrying out Edge Enhancement in a multiple beam pixel apparatus, applied to a multiple beam pixel apparatus with n input units, the apparatus being provided with (n+4) buffers and four static random access memories (SRAM), and the first nine rows of the (n+4) buffers being an operation block;
- the method comprising the following steps;
filling the operation block with serial data sequentially, wherein as for the first four columns of serial data in the operation block, since the first four buffers are all fully occupied, the serial data without being stored in each of the buffers are temporarily stored in the four SRAMs;
taking out n 9 by 5 tables for detecting required by the Edge Enhancement according to the arranging order of each of the buffers in the operation block;
carrying out the edge enhancement technology (EET) adjustment operation to the central pixels required to be edge enhanced in the n 9 by 5 tables;
outputing the n central pixel values being adjusted or with no need of being adjusted;
moving the serial data having already been read by the (n+4) buffers and the four SRAMs; and
reading the next bit data with each of the n input units.
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Accused Products
Abstract
A method for reducing memory consumption when carrying out edge enhancement in a multiple beam pixel apparatus is provided, wherein Static Random Access Memories and first in first out buffers are employed. When the first to the nth input units read the next bit data, the first rows of the bit data in the first to the nth buffers are removed, and each row of bit data behind the first rows is moved towards left by one bit. The first rows of bit data in the (n+1)th to the (n+4)th buffers are stored in one end of the first to the fourth memories respectively, and a bit data is taken out from the other end of each of the memories, to be sequentially stored in the end of the first to the fourth buffers, and the read next bit data is stored in the fifth to the (n+4)th buffers.
6 Citations
10 Claims
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1. A method for reducing memory consumption when carrying out Edge Enhancement in a multiple beam pixel apparatus, applied to a multiple beam pixel apparatus with n input units, the apparatus being provided with (n+4) buffers and four static random access memories (SRAM), and the first nine rows of the (n+4) buffers being an operation block;
- the method comprising the following steps;
filling the operation block with serial data sequentially, wherein as for the first four columns of serial data in the operation block, since the first four buffers are all fully occupied, the serial data without being stored in each of the buffers are temporarily stored in the four SRAMs;
taking out n 9 by 5 tables for detecting required by the Edge Enhancement according to the arranging order of each of the buffers in the operation block;
carrying out the edge enhancement technology (EET) adjustment operation to the central pixels required to be edge enhanced in the n 9 by 5 tables;
outputing the n central pixel values being adjusted or with no need of being adjusted;
moving the serial data having already been read by the (n+4) buffers and the four SRAMs; and
reading the next bit data with each of the n input units. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
- the method comprising the following steps;
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9. A method for generating a next table by moving serial data, suitable for sequentially generating n 9 by 5 tables for carrying out the EET operation when the first nine rows of the first buffer to the (n+4)th buffer are all filled with the serial data and the four SRAM have stored the serial data without being stored in each of the buffers, the method comprising the following steps:
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removing the first rows of bit data of the first buffer to the nth buffer;
storing the first rows of bit data of the (n+1)th buffer to the (n+4)th buffer in one end of each of the four SRAMs;
moving each row of bit data behind the first rows of the first buffer to the (n+4)th buffer towards left by one bit;
taking out a bit data from the other end of each of the four SRAMs, and storing them sequentially in the row at the end of the first buffer to the fourth buffer; and
storing the next bit data read by the first input unit to the nth input unit to the row at the end of the fifth buffer to the (n+4)th buffer sequentially. - View Dependent Claims (10)
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Specification