Nonvolative semiconductor memory device and operating method thereof

• US 20070140003A1
• Filed: 12/18/2006
• Published: 06/21/2007
• Est. Priority Date: 12/19/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Ido, Masamiti
• Granted Patent: US 7,495,955 B2
• Time in Patent Office: Days
• US Class Current: 365/185.200
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells for a user area and a trimming data storage area; and a plurality of word lines. A first trimming data is stored in the trimming data storage area, and is for adjusting a read voltage to be applied to a selected word line as one of the plurality of word lines in a read operation. The read voltage is set to a voltage which exceeds a maximum voltage in an adjustable voltage range based on the first trimming data when the read operation is carried out to the trimming data storage area.

Claims

1. A nonvolatile semiconductor memory device comprising:

a plurality of nonvolatile memory cells for a user area and a trimming data storage area; and

a plurality of word lines,

wherein a first trimming data is stored in said trimming data storage area, and is for adjusting a read voltage to be applied to a selected word line as one of said plurality of word lines in a read operation, and

said read voltage is set to a voltage which exceeds a maximum voltage in an adjustable voltage range based on said first trimming data when said read operation is carried out to said trimming data storage area.

2. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a sense amplifier configured to read a data based on a cell current which flows through said nonvolatile semiconductor memory cell and a reference current,

wherein a second trimming data to adjust said reference current is stored in said trimming data storage area,

said reference current is set to a current which exceeds a maximum current in an adjustable current range based on said second trimming data when said read operation is carried out to said trimming data storage area.

3. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a control section configured to generate a trimming read signal when the read operation is carried out to said trimming data storage area; and

a read voltage generating circuit comprising first to third resistances connected in series and first and second switch circuits, and configured to generate said read voltage in response to said first trimming data and said trimming read signal,

wherein said first switch circuit connects a first node between said first resistance and said second resistance to a ground voltage in response to said first trimming data, and

a second switch circuit connects a second node between said second resistance and said third resistance to the ground voltage in response to said trimming read signal.

4. The nonvolatile semiconductor memory device according to claim 2, further comprising:

a control section configured to generate a trimming read signal when the read operation is carried out to said trimming data storage area; and

a read voltage generating circuit comprising first to third resistances connected in series and first and second switch circuits, and configured to generate said read voltage in response to said first trimming data and said trimming read signal,

wherein said first switch circuit connects a first node between said first resistance and said second resistance to a ground voltage in response to said first trimming data, and

a second switch circuit connects a second node between said second resistance and said third resistance to the ground voltage in response to said trimming read signal.

5. A nonvolatile semiconductor memory device comprising:

a memory cell array having a plurality of nonvolatile memory cells;

a sense amplifier circuit configured to read a data from a selected memory cell which is selected from said plurality of nonvolatile memory cells based on a cell current and a reference current;

wherein said cell current flows through said selected memory cell and a bit line which is connected with said selected memory cell, based on a read voltage applied to a word line connected with said selected memory cell; and

a read voltage generating circuit configured to generate a first read voltage such that said cell current becomes larger than in a read operation from any of nonvolatile memory cells, in which a trimming data is not stored, of said plurality of nonvolatile memory cells, when said trimming data is read from said nonvolatile memory cells, in which said trimming data is stored, of said plurality of nonvolatile memory cells.

6. The nonvolatile semiconductor memory device according to claim 5, wherein said read voltage generating circuit generates said first read voltage higher than a second read voltage used to read another data when said selected memory cell is in a relatively low threshold voltage state, if a difference between said cell current and said reference current is less than a first current value as a lower limit current which said sense amplifier circuit can sense when to read said trimming data, In case of the read operation of said trimming data.

7. The nonvolatile semiconductor memory device according to claim 6, wherein said read voltage generating circuit comprises:

a reference word line voltage generating circuit configured to generate a second read voltage;

a first voltage changing circuit connected with said reference word line voltage generating circuit and configured to adjust an output of said reference word line voltage generating circuit to said first read voltage.

8. The nonvolatile semiconductor memory device according to claim 7, wherein said reference word line voltage generating circuit comprises:

an output stage transistor whose one end is connected with a constant voltage source and whose other end is connected to an output node, from which an output voltage is outputted;

a plurality of first resistances connected in series to form a series connection, and configured to resistance-divide a constant voltage supplied from said constant voltage source, wherein one end of said series connection is connected said output node;

an error amplification circuit configured to control a gate of said output stage transistor such that a difference between a first division voltage and said reference voltage is removed based on said first division voltage obtained from said constant voltage and said plurality of first resistances and said reference voltage; and

a first selecting circuit configured to select one of said plurality of first resistances to be used for the resistance division based on said trimming data, and

said first voltage changing circuit comprises a first switch whose one end is connected with a midway of said series connection, whose the other end is connected with the ground voltage, and which is turned on when said trimming data is read out.

9. The nonvolatile semiconductor memory device according to claim 5, further comprising:

a reference current generating circuit configured to generate said reference current such that said reference current becomes larger than in the read operation from said nonvolatile memory cells, in which said trimming data is not stored, in the read operation of said trimming data.

10. An operation method of a nonvolatile semiconductor memory device, which has a plurality of nonvolatile memory cells for a user area and a trimming data storage area, and a plurality of word lines, comprising:

a first trimming data is stored in said trimming data storage area to adjust a read voltage to be applied to a selected word line of said plurality of word lines in a read operation;

setting said read voltage to a voltage which exceeds a maximum voltage in an adjustable voltage range based on said first trimming data when the read operation is carried out to said trimming data storage area; and

applying said read voltage to said selected word line and executing the read operation to said trimming data storage area.

11. The operation method according to claim 10, wherein said nonvolatile semiconductor memory device comprises a sense amplifier configured to read a data based on a cell current and a reference current which flows through one of said plurality of nonvolatile memory cells connected with said selected word line,

a second trimming data to adjust said reference current is stored in said trimming data storage area,

said operation method further comprises:

setting said reference current to a current which exceeds a maximum current in an adjustable current range based on said second trimming data before said applying said read voltage.

12. An operation method of a nonvolatile semiconductor memory device, which comprises a cell array containing a plurality of nonvolatile memory cells, a sense amplifier configured to read a data from a selected memory cell selected from said plurality of nonvolatile memory cells based on a cell current and a reference current, wherein said cell current flows through a bit line connected with said selected memory cell and said selected memory cell based on said read voltage applied to said word line which connected with said selected memory cell, and a read voltage generating circuit configured to generate said read voltage, said operation method comprising:

generating a first read voltage such that said cell current becomes larger than in the read operation from said selected memory cell, in which said trimming data is not stored, from said plurality of nonvolatile memory cells, when said read voltage generating circuit reads said trimming data from said selected memory cells, in which said trimming data are stored, from said plurality of nonvolatile memory cells; and

said sense amplifier reading said trimming data from said selected memory cells based on said cell current and said the reference current.

13. The operation method according to claim 12, wherein said generating a first read voltage comprises:

said voltage generating circuit setting said first read voltage to a voltage higher than a second read voltage used to read other data when said selected memory cell is in a first state as a relatively low threshold voltage state, if a difference between said cell current and said reference current is less than a first current as a lower limit current which can be read by said sense amplifier, in the read operation of said trimming data.

14. The operation method according to claim 12, wherein said generating a first read voltage is executed in a reset sequence.