Semiconductor memory with redundant replacement for elements posing future operability concern

• US 20070141731A1
• Filed: 12/20/2005
• Published: 06/21/2007
• Est. Priority Date: 12/20/2005
• Status: Abandoned Application

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Chen, Jian, Tu, Loc, Hemink, Gerrit, Ponnuru, Kiran
• Application Number:
  US11/316,108
• Publication Number:
  US 20070141731A1
• Time in Patent Office: Days
• US Class Current: 438/14
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Future operability predictor testing is incorporated into the fabrication of integrated circuits that utilize redundancy. Select reliability testing can be used to identify circuit elements such as memory cells that fail or become defective over time. Future operability tests and associated stress conditions are then developed for application during the fabrication process to identify memory cells that may pose a future operability concern before they actually fail. Memory cells that are determined to pose a future operability concern are replaced by redundant memory cells.

Claims

1. A method of manufacturing integrated circuits, comprising:

testing a plurality of circuit devices by applying at least one functionality test and at least one future operability test, said circuit devices include a plurality of primary storage elements and a plurality of redundant storage elements; and

replacing primary storage elements that pass said at least one functionality test but fail said at least one future operability test with redundant storage elements of said circuit devices.

2. The method of claim 1, wherein:

said testing is wafer level testing; and

said circuit devices are memory chips on a wafer, each memory chip including at least one memory array.

3. The method of claim 1, wherein:

said testing is package level testing; and

said circuit devices are packaged memory devices, wherein each packaged memory device includes at least one chip having at least one memory array.

4. The method of claim 3, wherein each of said packaged memory devices further includes a controller in communication with said at least one chip.

5. The method of claim 1, wherein said plurality of circuit devices is a first plurality of circuit devices, said method further comprising:

testing a second plurality of circuit devices by applying at least one reliability test;

identifying a storage element failure resulting from said at least one reliability test;

formulating said at least one future operability test based on said at least one reliability test and said storage element failure, said formulating includes designing said at least one future operability test to identify functional storage elements that may experience said storage element failure prior to said storage element failure occurring in said functional storage elements.

6. The method of claim 5, wherein:

said at least one future operability test includes a test and a stress condition; and

formulating said at least one future operability test includes formulating said test and said stress condition based on said at least one reliability test and said storage element failure.

7. The method of claim 5, wherein:

said circuit devices of said first plurality each include a plurality of bit lines;

said memory element failure is a shorted bit line;

said at least one future operability test determines whether any of said bit lines has a leakage current above a predetermined level;

replacing primary storage elements that fail said at least one future operability test includes replacing at least one primary storage element associated with a bit line having a leakage current above said predetermined level.

8. The method of claim 1, wherein:

testing by applying said at least one future operability predictor test includes identifying functional but weaker storage elements with greater susceptibility to program disturb than other storage elements of said plurality of circuit devices.

9. The method of claim 1, wherein:

said plurality of primary storage elements and said plurality of redundant storage elements are organized into a plurality of NAND strings.

10. The method of claim 1, wherein:

said plurality of primary storage elements and said plurality of redundant storage elements are multi-state flash memory cells.

11. A method of manufacturing integrated circuits, comprising:

testing a plurality of circuit devices by applying at least one functionality test and at least one future operability test, said circuit devices include a plurality of primary storage elements and a plurality of redundant storage elements; and

replacing primary storage elements that fail said at least one future operability test with redundant storage elements of said circuit devices.

12. The method of claim 11, wherein replacing primary storage elements that fail said at least one future operability test comprises:

replacing primary storage elements that fail said at least one future operability test but pass said at least one functionality test with redundant storage elements of said circuit devices.

13. The method of claim 11, wherein:

said testing is wafer level testing; and

said circuit devices are memory chips on a wafer, each memory chip including at least one memory array.

14. The method of claim 11, wherein:

said testing is package level testing; and

said circuit devices are packaged memory devices, wherein each packaged memory device includes at least one chip having at least one memory array.

15. The method of claim 11, wherein said plurality of circuit devices is a first plurality of circuit devices, said method further comprising:

testing a second plurality of circuit devices by applying at least one reliability test;

identifying a storage element failure resulting from said at least one reliability test;

formulating said at least one future operability test based on said at least one reliability test and said storage element failure, said formulating includes designing said at least one future operability test to identify functional storage elements that may experience said storage element failure prior to said storage element failure occurring in said functional storage elements.

16. The method of claim 11, wherein:

said plurality of primary storage elements and said plurality of redundant storage elements are organized into a plurality of NAND strings.

17. A method of manufacturing integrated circuits, comprising:

applying a reliability test to a first plurality of packaged circuit devices;

detecting a failure associated with a portion of one or more packaged circuit devices of said first plurality after applying said reliability test;

formulating a future operability predictor test in response to said applying and detecting, said future operability predictor test is formulated to detect a potential for said failure in a second plurality of circuit devices, each circuit device of said second plurality includes primary storage elements and redundant storage elements;

applying said future operability predictor test to said second plurality of circuit devices; and

replacing selected primary storage elements of said second plurality of circuit devices with redundant storage elements of said second plurality of circuit devices based on a result of said future operability predictor test.

18. The method of claim 17, wherein:

said second plurality of circuit devices is a second plurality of packaged circuit devices; and

said future operability predictor test is applied during package level testing of said second plurality of packaged devices.

19. The method of claim 17, wherein:

said second plurality of circuit devices is a second plurality of pre-packaging memory chips that each include at least one memory array;

said future operability predictor test is applied during wafer level testing of said second plurality of pre-packaging memory chips.

20. The method of claim 17, wherein:

replacing primary storage elements includes replacing at least one primary storage element that is determined to be functional with a redundant storage element.

21. The method of claim 17, wherein:

said primary storage elements and said redundant storage elements are binary flash memory cells.

22. A method of manufacturing integrated circuits, comprising:

testing at least one wafer including a plurality of memory chips, each of said memory chips including primary storage elements and redundant storage elements, said testing includes replacing primary storage elements that fail functionality testing with redundant storage elements;

creating a packaged memory device from one or more of said memory chips;

stressing said packaged memory device;

testing said packaged memory device by applying at least one functionality test and at least one future operability predictor test; and

replacing primary storage elements of said packaged memory device that pass said at least one functionality test but fail said at least one future operability predictor test with redundant storage elements of said packaged memory device.

23. The method of claim 22, wherein:

stressing said packaged memory device includes applying at least one condition to said packaged memory device that is designed to cause an indication for ones of said primary storage elements that pose a future operability concern;

applying said at least one future operability predictor test includes detecting said indication in said ones of said primary storage elements that pose a future operability concern.

24. The method of claim 22, wherein testing said at least one wafer includes:

applying at least one functionality test and at least one future operability predictor test; and

replacing primary storage elements of said at least one wafer that pass said at least one functionality test but fail said at least one future operability test with redundant storage elements.

25. The method of claim 22, wherein:

said primary storage elements are multi-state flash memory cells.

26. A method of manufacturing integrated circuits, comprising:

testing whether at least a portion of a circuit device is functional, said circuit device including primary storage elements and redundant storage elements;

replacing primary storage elements that are determined not to be functional with redundant storage elements;

testing whether primary storage elements of said circuit device that are determined to be functional may pose a future operability concern; and

replacing with redundant storage elements those primary storage elements of said circuit device that are determined to be functional but pose a future operability concern.

27. The method of claim 26, wherein:

said circuit device is a memory chip on a wafer; and

testing whether at least a portion of said circuit device is functional and testing whether primary memory elements of said circuit device that are determined to be functional may pose a future operability concern are both performed during wafer level testing of said wafer.

28. The method of claim 26, wherein:

said circuit device is a packaged memory device including at least one memory chip; and

testing whether at least a portion of said circuit device is functional and testing whether primary memory elements of said circuit device that are determined to be functional may pose a future operability concern are both performed during package level testing for said packaged memory device.

29. The method of claim 26, wherein testing whether primary storage elements of said circuit device that are determined to be functional may pose a future operability concern includes:

applying at least one condition to said circuit device designed to cause an indication for ones of said functional primary storage elements that may pose a future operability concern; and

determining whether said indication is present for said functional primary storage elements.

30. The method of claim 26, wherein said circuit device is a first circuit device, said method further comprising:

testing a second circuit device by applying at least one reliability test;

identifying a failure associated with said second circuit device resulting from said at least one reliability test; and

formulating said at least one future operability test based on said at least one reliability test and said failure associated with said second circuit device, said formulating includes designing said at least one future operability test to identify functional storage elements that may experience said failure prior to said failure occurring.

31. The method of claim 30, wherein:

said at least one future operability test includes a test and a stress condition; and

formulating said at least one future operability test includes formulating said test and said stress condition based on said at least one reliability test and said failure associated with said second circuit device.

32. The method of claim 26, wherein:

said primary storage elements are organized into a plurality of NAND strings.