Trench field effect transistor and method of making it

• US 20070141783A1
• Filed: 02/23/2005
• Published: 06/21/2007
• Est. Priority Date: 03/03/2004
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Peake, Steven
• Granted Patent: US 7,682,889 B2
• Time in Patent Office: Days
• US Class Current: 438/259
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618

Abstract

A method of manufacturing an insulated gate field effect transistor includes providing a substrate (2) having a low-doped region (4), forming insulated gate trenches (8) and implanting dopants of a first conductivity type at the base of the trenches (8). A body implant is implanted in the low-doped regions between the trenches; and diffused to form an insulated gate transistor structure in which the body implant diffuses to form a p-n junction between a body region (22) doped to have the second conductivity type above a drain region (20) doped to have the first conductivity type, the p-n junction being deeper below the first major surface between the trenches than at the trenches. The difference in doping concentration between the low-doped region (4) and the implanted region at the base of the trenches causes the difference in depth of the body-drain p-n junction formed in the diffusion step.

Claims

1. A method of manufacturing an insulated gate field effect transistor;

including;

providing a substrate having a first major surface having a low-doped region at the first major surface, the low-doped region having a concentration of less than 5×

10¹⁴ cm<sup>−

3</sup> at the first major surface;

forming gate trenches extending from the first major surface;

forming trench insulator on the base and sidewalls of the gate trenches;

implanting dopants of a first conductivity type at the base of the trenches;

implanting a body implant of second conductivity type opposite to the first conductivity type in the low-doped regions between the trenches;

carrying out a diffusion step to form an insulated gate transistor structure in which the body implant diffuses towards the substrate in the low doped region to form a p-n junction between a body region doped to have the second conductivity type above a drain region doped to have the first conductivity type, the p-n junction being deeper below the first major surface between the trenches than at the trenches; and

forming source regions at the first major surface adjacent to the trench.

2. A method according to claim 1 in which the p-n junction boundary between drain and body is deeper between the trenches than the depth of the trenches.

3. A method according claim 1 in which the structure formed in the diffusion step has an additionally doped region of first conductivity type at the base of the gate trenches having a doping density below 5×

10¹⁶ cm<sup>−

3</sup> but higher than in the drain regions between the trenches.

4. A method according claim 1, wherein the step of implanting a body implant implants the body implant has a dose of at most 5×

10¹³ cm<sup>−

2</sup>.

5. A method according to claim 1 further comprising the step of,

forming a pattern laterally across the first major surface of the substrate, the pattern doped to have lower-doped regions of first conductivity type alternating with higher-doped regions of first conductivity type,

wherein the gate trenches (10) are formed in the higher-doped regions.

6. A method according to claim 5 wherein:

the step of forming a pattern laterally across the first major surface of the substrate includes;

depositing an epilayer of semiconductor doped to have a lower doping density;

patterning a plurality of trench etch windows spaced laterally across the substrate; and

implanting dopants though the trench etch windows, the dopants being of a first conductivity type;

wherein the step of forming gate trenches in the higher doped regions includes etching gate trenches through the trench etch windows.

7. A method according to claim 5 wherein the step of forming a pattern laterally across the first major surface of the substrate includes:

etching a plurality of semiconductor trenches spaced laterally across the substrate in a layer of lower doping density; and

growing semiconductor doped to have a higher doping density in the semiconductor trenches.

8. A method according to claim 1, wherein the semiconductor is silicon and the first conductivity type is n-type.

9. A method according to claim 1, for making an insulating gate transistor of predetermined breakdown voltage for which the doping of a an epilayer for forming a conventional insulated gate field effect transistor without the step of implanting dopant at the gate of the trench has a first predetermined doping concentration;

wherein the doping of the low doped region at the first major surface is at most one half of the predetermined doping concentration.

10. A method according to claim 1, further comprising performing a moat etch by etching the semiconductor away from the trenches to a depth below the bottom of the source region.

11. A trench FET formed by the method of claim 1.