Transistor structures and methods for making the same

• US 20070141784A1
• Filed: 02/05/2007
• Published: 06/21/2007
• Est. Priority Date: 05/21/2002
• Status: Active Grant

• Current Assignee: Oregon State University (Oregon University System)
• Original Assignee: Oregon State University (Oregon University System)
• Inventors: Hoffman, Randy, Wager, John
• Granted Patent: US 7,888,207 B2
• Time in Patent Office: Days
• US Class Current: 438/261
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Enhancement mode, field effect transistors wherein at least a portion of the transistor structure may be substantially transparent. One variant of the transistor includes a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO or SnO₂. A gate insulator layer comprising a substantially transparent material is located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface. A second variant of the transistor includes a channel layer comprising a substantially transparent material selected from substantially insulating ZnO or SnO₂, the substantially insulating ZnO or SnO₂ being produced by annealing. Devices that include the transistors and methods for making the transistors are also disclosed.

Claims

1. A method for making an enhancement mode, field effect transistor comprising:

depositing ZnO or SnO₂ onto at least a portion of a surface of a gate insulating layer; and

annealing the ZnO or SnO₂ for about 1 to about 5 minutes at a temperature of about 300 to about 1000°

C. in an oxidative or inert atmosphere.

2. The method according to claim 1, wherein ZnO is deposited.

3. The method according to claim 1, wherein SnO₂ is deposited and the method further comprises introducing an acceptor dopant into the SnO₂.

4. The method according to claim 1, wherein the gate insulator layer comprises a substantially transparent material.

5. The method according to claim 1, wherein the annealing temperature is about 700 to about 800°

C.

6. The method according to claim 1, further comprising depositing on the ZnO or SnO₂ layer at least one material for forming a source and a drain.

7. The method according to claim 1, further comprising depositing on the gate insulating layer at least one material for forming a source and a drain prior to depositing the ZnO or SnO₂.

8. The method according to claim 7, wherein the material for forming a source and a drain is ion beam sputtered deposited onto the gate insulating layer, and the annealing of the ZnO diffusion dopes the ZnO with the source and drain material.

9. The method according to claim 6, further comprising annealing the source and drain material.

11. The method according to claim 2, wherein the ZnO is vapor deposited.

13. The method according to claim 11, wherein the ZnO is chemical vapor deposited or sputtered.

15. The method according to claim 1, wherein the field effect transistor exhibits an optical transmission through the field effect transistor of at least about 70% in the visible portion of the electromagnetic spectrum.

16. The method according to claim 1, wherein the ZnO is not doped.

17. The method according to claim 3, wherein the SnO₂ is vapor deposited.

18. The method according to claim 1, wherein the ZnO or SnO₂ is annealed in an oxidative atmosphere.

19. The method according to claim 1, wherein the ZnO or SnO₂ is annealed in an inert atmosphere.

20. The method according to claim 1, wherein the deposited and annealed ZnO or SnO₂ forms a substantially insulating, substantially transparent, material.

10. A method for making an enhancement mode, field effect transistor comprising:

depositing ZnO or SnO₂ onto at least a portion of a surface of a gate insulating layer; and

treating the ZnO or SnO₂ such that the treated ZnO or SnO₂ has a higher resistivity and a lower oxygen vacancy concentration relative to the untreated ZnO or SnO₂.

12. The method according to claim 10, wherein ZnO is vapor deposited.

14. The method according to claim 12, wherein the ZnO is chemical vapor deposited or sputtered.