MICROELECTROMECHANICAL SYSTEM PRESSURE SENSOR AND METHOD FOR MAKING AND USING

• US 20070141808A1
• Filed: 02/22/2007
• Published: 06/21/2007
• Est. Priority Date: 09/20/2004
• Status: Active Grant

• Current Assignee: Amphenol Thermometrics, Inc. (Amphenol Corporation)
• Original Assignee: General Electric Company
• Inventors: Subramanian, Kanakasabapathi, Wu, Guanghua, Fortin, Jeffrey
• Granted Patent: US 7,563,692 B2
• Time in Patent Office: Days
• US Class Current: 438/459
• CPC Class Codes: G01L 1/148 using semiconductive material, e.g. silicon
• CPC Class Codes: G01L 9/0073 using a semiconductive diaphragm

Abstract

According to some embodiments, a conducting layer is formed on a first wafer. An insulating layer is formed on a second wafer. The insulating layer includes a cavity and a conducting area may be formed in the second wafer proximate to the cavity. The side of the conducting layer opposite the first wafer is bonded to the side of the insulating layer opposite the second wafer. At least some of the first wafer is then removed, without removing at least some of the conducting layer, to form a conducting diaphragm that is substantially parallel to the second wafer. In this way, an amount of capacitance between the diaphragm and the conducting area may be measured to determine an amount of pressure being applied to the diaphragm.

Claims

1. A method, comprising:

forming a conducting layer on a first wafer;

forming an insulating layer on a second wafer, wherein the insulating layer includes a cavity;

bonding a side of the conducting layer opposite the first wafer to a side of the insulating layer opposite the second wafer; and

removing at least a portion of the first wafer without removing at least a portion of the conducting layer associated with the cavity to form a diaphragm substantially parallel to the second wafer.

2. The method of claim 1, further comprising prior to said bonding:

forming a conducting area in the second wafer proximate to the cavity.

3. The method of claim 2, wherein the second wafer is a lightly doped silicon wafer and said forming the conducting area comprises:

creating a highly doped area in the second wafer via at least one of (i) diffusion or (ii) ion bombardment.

4. The method of claim 3, further comprising:

forming a non-conducting protective layer over the highly doped area.

5. The method of claim 1, wherein the first wafer comprises a lightly doped silicon wafer.

6. The method of claim 5, wherein said forming the conducting layer comprises:

epitaxially growing a highly doped layer on the first wafer, wherein the surface of the highly doped layer opposite the first wafer is substantially smooth.

7. The method of claim 1, wherein the first wafer comprises at least one of:

(i) a silicon wafer or (ii) a silicon on insulator wafer.

8. The method of claim 7, wherein said forming the insulating layer comprises:

creating an oxide layer on the second wafer via at least one of (i) growing the oxide layer and (ii) deposing the oxide layer, wherein the surface of the oxide layer opposite the second wafer is substantially smooth.

9. The method of claim 8, wherein said forming the insulating layer further includes:

creating the cavity using a pattern mask and a potassium hydroxide wash.

10. The method of claim 1, wherein the insulating layer further includes a reference cavity.

11. The method of claim 1, wherein the diaphragm is associated with a microelectromechanical capacitive pressure sensor.

12-24. -24. (canceled)