Low temperature doped silicon layer formation

• US 20070141812A1
• Filed: 12/14/2006
• Published: 06/21/2007
• Est. Priority Date: 12/16/2005
• Status: Active Grant

• Current Assignee: ASM International NV
• Original Assignee: ASM International NV
• Inventors: Zagwijn, Peter, Fischer, Pamela, Oosterlaken, Theodorus Gerardus, Van Aerde, Steven
• Granted Patent: US 7,718,518 B2
• Time in Patent Office: Days
• US Class Current: 438/479
• CPC Class Codes: C23C 16/24 Deposition of silicon only
• CPC Class Codes: C23C 16/45523 Pulsed gas flow or change of composition over time
• CPC Class Codes: C23C 16/45578 Elongated nozzles, tubes with holes
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/06 Silicon
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD

Abstract

A doped silicon layer is formed in a batch process chamber at low temperatures. The silicon precursor for the silicon layer formation is a polysilane, such as trisilane, and the dopant precursor is an n-type dopant, such as phosphine. The silicon precursor can be flowed into the process chamber with the flow of the dopant precursor or separately from the flow of the dopant precursor. Surprisingly, deposition rate is independent of dopant precursor flow, while dopant incorporation linearly increases with the dopant precursor flow.

Claims

1. A method of semiconductor processing, comprising:

depositing a silicon layer on a plurality of substrates in a batch process chamber by exposing the substrates to trisilane; and

doping the silicon layer by exposing the substrates to an n-type dopant precursor during at least part of the deposition of the silicon layer.

2. The method of claim 1, wherein depositing the silicon layer comprises maintaining reaction rate limited deposition conditions in the process chamber.

3. The method of claim 1, wherein depositing the silicon layer and doping the silicon layer is performed at a temperature of about 600°

C. or less.

4. The method of claim 3, wherein the temperature less than about 500°

C.

5. The method of claim 3, wherein the temperature is about 430°

C. to about 500°

C.

6. The method of claim 5, wherein the deposition rate is greater than 1 Å

/min for any temperature from about 430°

C. to about 500°

C.

7. The method of claim 1, wherein the dopant precursor is a hydride.

8. The method of claim 7, wherein the dopant precursor is PH₃.

9. The method of claim 7, wherein the dopant precursor is AsH₃.

10. The method of claim 1, wherein an as-deposited surface roughness of the deposited in-situ doped silicon layer is greater than a substrate surface roughness by about 5 Å

rms or less.

11. The method of claim 10, wherein the as-deposited surface roughness is greater than the substrate surface roughness by an amount of about 3 Å

rms or less.

12. The method of claim 11, wherein the as-deposited surface roughness is greater than the substrate surface roughness by an amount of about 2 Å

rms or less.

13. The method of claim 1, wherein doping the silicon layer results in a doping level of about 4.00×

10²⁰ atoms/cm³ or more.

14. The method of claim 13, wherein the doping level is about 5.00×

10²⁰ atoms/cm³.

15. The method of claim 13, wherein a 1σ

-uniformity of the doping level is about 1% or less.

16. The method of claim 1, wherein a 1σ

-uniformity of a thickness of the layer is about 1% or less.

17. The method of claim 1, wherein depositing the silicon layer and doping the silicon layer form a doped silicon layer having a thickness of about 150 Å

or less.

18. The method of claim 17, wherein the thickness is about 100 Å

or less.

19. The method of claim 1, wherein less than 20 particles having a size of about 0.12 μ

m or greater are added per substrate.

20. The method of claim 19, wherein less than 10 particles having a size of about 0.12 μ

m or greater are added per substrate.

21. A method for forming an integrated circuit, comprising doping a silicon layer while depositing the silicon layer in a batch process chamber using trisilane as a silicon precursor, wherein, under the selected deposition conditions, a deposition rate of the silicon layer is substantially independent of a flow rate of the dopant precursor for any dopant precursor flow rate between about 0 sccm and about 160 sccm.

22. The method of claim 21, wherein the dopant precursor is phosphine.

23. The method of claim 21, wherein the dopant precursor comprises germanium.

24. The method of claim 23, wherein the dopant precursor is germane.

25. The method of claim 21, wherein an incorporation of dopant into the silicon layer is substantially linear as a function of a partial pressure of the dopant in the process chamber.

26. The method of claim 21, wherein doping the silicon layer is performed at less than about 475°

C.

27. The method of claim 21, wherein the deposition rate is greater than about 1 Å

/min.

28. The method of claim 21, wherein depositing the silicon layer comprises forming a substantially completely continuous film before the silicon layer reaches a thickness of about 40 Å

.

29. The method of claim 21, wherein depositing the silicon layer comprises flowing trisilane into the process chamber from a vertical injector, the vertical injector comprising a plurality of vertically distributed openings.

30. A system for processing semiconductor substrates, comprising:

a batch process chamber configured to accommodate a plurality of semiconductor substrates;

a source of trisilane in gas communication with the batch process chamber;

a source of dopant precursor in gas communication with the batch process chamber; and

a controller programmed to flow the trisilane and the dopant precursor into the process chamber to form as-deposited doped silicon layers on the substrates.

31. The system of claim 30, wherein the controller is programmed to establish reaction rate limited deposition conditions within the process chamber.

32. The system of claim 30, wherein the controller is programmed to flow the trisilane and the dopant precursor while maintaining a process chamber temperature of about 600°

C. or less.

33. The method of claim 32, wherein the temperature is less than about 500°

C.

34. The method of claim 33, wherein the temperature is about 430°

C. to about 500°

C.

35. The system of claim 30, wherein the source of the dopant precursor comprises phosphine.

36. The system of claim 30, wherein the source of the dopant precursor comprises AsH₃.

37. The system of claim 30, wherein the process chamber is a vertical furnace.

38. The system of claim 37, further comprising a wafer boat configured to accommodate the substrates with the substrates spaced apart vertically and having major substrate surfaces oriented horizontally.

39. The system of claim 37, further comprising a vertical injector connected to the source of trisilane and disposed inside the process chamber, the vertical injector comprising a plurality of vertically distributed openings for releasing gas into the process chamber.

40. The system of claim 37, wherein the vertical injector is further connected to the source of dopant precursor.

41. The system of claim 30, wherein the dopant precursor is comprises an n-type dopant.

42. The system of claim 30, wherein the controller is programmed to simultaneously flow trisilane and the dopant precursor into the process chamber.