Methods of fabricating isolation regions of semiconductor devices and structures thereof

• US 20070141852A1
• Filed: 12/20/2005
• Published: 06/21/2007
• Est. Priority Date: 12/20/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Tilke, Armin, Stapelmann, Chris
• Granted Patent: US 8,501,632 B2
• Time in Patent Office: Days
• US Class Current: 438/758
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/02348 treatment by exposure to UV light
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence

Abstract

Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. A preferred embodiment includes forming at least one trench in a workpiece, and forming a thin nitride liner over sidewalls and a bottom surface of the at least one trench and over a top surface of the workpiece using atomic layer deposition (ALD). An insulating material is deposited over the top surface of the workpiece, filling the at least one trench. At least a portion of the insulating material is removed from over the top surface of the workpiece. After removing the at least a portion of insulating material from over the top surface of the workpiece, the thin nitride liner in the at least one trench is at least coplanar with the top surface of the workpiece. The thin nitride liner and the insulating material form an isolation region of the semiconductor device.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

providing a workpiece, the workpiece having a top surface;

forming at least one trench in the workpiece, the at least one trench comprising sidewalls and a bottom surface;

forming a thin nitride liner over the sidewalls and the bottom surface of the at least one trench and over the top surface of the workpiece using atomic layer deposition (ALD);

depositing an insulating material over the top surface of the workpiece, filling the at least one trench with the insulating material; and

removing at least a portion of the insulating material from over the top surface of the workpiece, wherein after removing the at least a portion of insulating material from over the top surface of the workpiece, the thin nitride liner in the at least one trench is at least coplanar with the top surface of the workpiece, and wherein the thin nitride liner and the insulating material form an isolation region of the semiconductor device.

2. The method according to claim 1, wherein forming the thin nitride liner comprises forming a liner that is continuous and has a thickness of about 25 Angstroms or less.

3. The method according to claim 1, wherein forming the thin nitride liner comprises forming Si₃N₄, Si_xN_y, or Si₃N₄ or Si_xN_y combined with about 1% or less of hydrogen.

4. The method according to claim 3, further comprising forming a sacrificial material layer over the workpiece, before forming the at least one trench in the workpiece, wherein forming the at least one trench in the workpiece further comprises forming the at least one trench in the sacrificial material layer, wherein forming the thin nitride liner further comprises forming the thin nitride liner over sidewalls of the sacrificial material layer and over a top surface of the sacrificial material layer, further comprising removing at least a portion of the sacrificial material layer, after filling the at least one trench with the insulating material.

5. The method according to claim 1, wherein the top surface of the workpiece comprises a first height, wherein after removing the at least a portion of the insulating material from over the top surface of the workpiece, the insulating material comprises a second height over the at least one trench, wherein the second height is greater than or equal to the first height of the top surface of the workpiece.

6. The method according to claim 5, wherein the second height differs from the first height by about 0 to 40 nm.

7. A method of forming an isolation region of a semiconductor device, the method comprising:

providing a workpiece;

forming a pad oxide over the workpiece;

forming a pad nitride over the pad oxide;

forming at least one trench in the pad nitride, the pad oxide, and the workpiece;

forming an oxide liner over at least a portion of the at least one trench formed in the workpiece;

forming a thin nitride liner over the at least one trench and over the oxide liner using atomic layer deposition (ALD);

depositing an oxide material to fill the at least one trench with the oxide material, wherein a first portion of the oxide material resides above a bottom surface of the pad nitride, and wherein a second portion of the oxide material resides above a top surface of the workpiece;

removing the pad nitride;

removing the first portion of the oxide material from over the bottom surface of the pad nitride; and

removing at least a portion of the second portion of the oxide material from over the top surface of the workpiece, wherein after removing the at least a portion of the second portion of the oxide material from over the top surface of the workpiece, the thin nitride liner is at least coplanar with the top surface of the workpiece, and wherein the thin nitride liner, the oxide liner, and the insulating material form an isolation region of the semiconductor device.

8. The method according to claim 7, wherein forming the thin nitride liner comprises forming a liner that is continuous and comprises a thickness of about 25 Angstroms or less.

9. The method according to claim 7, wherein forming the pad nitride and the thin nitride liner comprise forming silicon nitride, and wherein forming the pad oxide, the oxide liner, and the oxide material comprise forming silicon dioxide.

10. The method according to claim 7, further comprising forming at least two active areas in the workpiece, wherein forming the at least one trench comprises forming a trench between the at least two active areas, and wherein depositing the oxide material comprises forming a shallow trench isolation (STI) region between the at least two active areas.

11. The method according to claim 7, further comprising treating the thin nitride liner with a UV process, a plasma process, a heat process, or combinations thereof, after forming the thin nitride liner.

12. The method according to claim 11, wherein treating the thin nitride liner alters the tensile or compressive stress of the thin nitride liner.

13. The method according to claim 11, further comprising forming at least two active areas in the workpiece, wherein forming the at least one trench comprises forming a trench between the at least two active areas, wherein depositing the oxide material comprises forming a shallow trench isolation (STI) region between the at least two active areas, and wherein treating the thin nitride liner improves the performance of the active areas.

14. A method of forming an isolation region of a semiconductor device, the method comprising:

providing a workpiece, the workpiece having a top surface;

forming a sacrificial material layer over the workpiece;

forming at least one trench in the sacrificial material layer and the workpiece, the at least one trench comprising sidewalls and a bottom surface;

forming a first liner over at least the sidewalls and the bottom surface of the at least one trench in the workpiece;

forming a second liner over at least the first liner using atomic layer deposition (ALD);

filling the at least one trench with an insulating material, wherein a portion of the insulating material resides over the top surface of the workpiece;

removing at least a portion of the sacrificial material layer from over the workpiece; and

removing the portion of the insulating material from over the top surface of the workpiece, wherein after removing the portion of the insulating material from over the top surface of the workpiece, at least the second liner is at least coplanar with the top surface of the workpiece, and wherein the second liner, the first liner, and the insulating material form an isolation region of the semiconductor device.

15. The method according to claim 14, wherein forming the second liner comprises forming the second liner using rapid ALD.

16. The method according to claim 14, wherein at least a portion of the sacrificial material layer comprises a pad nitride layer comprising silicon nitride, wherein forming the second liner comprises forming silicon nitride, and wherein removing at least the portion of the sacrificial material from over the workpiece comprises removing the pad nitride layer.

17. The method according to claim 14, wherein forming the second liner comprises forming a continuous liner having a thickness of about 25 Angstroms or less.

18. The method according to claim 14, wherein at least a portion of the sacrificial material layer comprises a pad oxide layer comprising silicon dioxide, wherein forming the first liner comprises forming silicon dioxide, and wherein filling the at least one trench with the insulating material comprises filling the trench with silicon dioxide.

19. The method according to claim 14, wherein after removing the portion of the insulating material from over the top surface of the workpiece, the first liner and the insulating material are at least coplanar with the top surface of the workpiece.

20. A semiconductor device, comprising:

a workpiece, the workpiece having a top surface;

at least one trench formed in the workpiece, the at least one trench comprising sidewalls and a bottom surface;

a thin nitride liner disposed over the sidewalls and the bottom surface of the at least one trench, the thin nitride liner being continuous and comprising a thickness of about 25 Angstroms or less; and

an insulating material disposed over the thin nitride liner within the trench, wherein the thin nitride liner is at least coplanar with the top surface of the workpiece, and wherein the thin nitride liner and the insulating material comprise an isolation region of the semiconductor device.

21. The semiconductor device according to claim 20, wherein the thin nitride liner comprises Si₃N₄, Si_xN_y, or Si₃N₄ or Si_xN_y combined with about 1% or less of hydrogen.

22. The semiconductor device according to claim 20, wherein the thin nitride liner comprises a single monolayer of nitride molecules, or 2 to 10 monolayers of nitride molecules.

23. The semiconductor device according to claim 20, wherein the insulating material comprises silicon dioxide.

24. The semiconductor device according to claim 20, further comprising a thin oxide liner disposed over the sidewalls and the bottom surface of the at least one trench, beneath the thin nitride liner.