Power loss recovery for bit alterable memory

• US 20070143531A1
• Filed: 12/15/2005
• Published: 06/21/2007
• Est. Priority Date: 12/15/2005
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Atri, Sunil
• Application Number:
  US11/303,238
• Publication Number:
  US 20070143531A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges

Abstract

A bit alterable memory device may include status bits such as a direction bit and two register bits for a colony of memory cells. The state of each status bit may be changed depending on the programming state of the non-volatile bit alterable memory. The status bits may be examined to determine the write status of two separate colonies of memory cells in the event of a power loss. The information gathered from the status bits can be used by a power loss recovery mechanism to determine whether the data written to a plurality of memory cell colonies is partially written. Applying a power loss recovery mechanism to a bit alterable memory can prevent the user from relying on data that is corrupt or otherwise unusable.

Claims

1. A method comprising:

providing a direction bit and at least two register bits for a plurality of cell colonies in a bit alterable memory; and

determining a programming state of the plurality of cell colonies based on the direction bit and the register bits.

2. The method of claim 1 wherein at least one of the register bits contains a grey code.

3. The method of claim 1 wherein the method is used for power loss recovery.

4. The method of claim 1, further comprising configuring a number of cells in each of the plurality of cell colonies.

5. The method of claim 1 further comprising determining whether the direction bit is at a first state or a second state in response to reading the direction bit.

6. The method of claim 5 wherein if the direction bit is at the first state, designating that a first memory cell colony is valid.

7. The method of claim 5 wherein if the direction bit is at the first state and each of the register bits is at the first state, designating that a first memory cell colony is valid and at least one of the plurality of cell colonies is invalid.

8. The method of claim 5 wherein if the direction bit and one register bit is at the first state and at least one register bit is at the second state, designating that the programming operation is not complete.

9. The method of claim 5 wherein if all register bits are at the second state, designating that at least one of the plurality of cell colonies is updated.

10. The method of claim 5, wherein if the direction bit is at the second state, designating that a second memory cell colony is valid.

11. The method of claim 5, wherein if the direction bit is at the second state and each of the register bits is at second state, designating that second memory cell colony is valid and at least one of the plurality of cell colonies is invalid.

12. The method of claim 5, wherein if the direction bit and one register bit is at the second state and at least one register bit is at the first state, designating that the programming operation is not complete.

13. The method of claim 5, wherein if the register bits are not at the second state, designating that at least one of the plurality of cell colonies is updated.

14. An article comprising a medium storing instructions that enable a system to:

provide a direction bit and at least two register bits for a plurality of cell colonies in a bit-alterable memory; and

determining a programming state of the plurality of cell colonies based on the direction bit and the register bits.

15. The article of claim 14, wherein at least one of the register bits contains a grey code.

16. The article of claim 14, wherein the article is used for power loss recovery.

17. A system comprising:

a bit alterable memory comprising a plurality of cell colonies having at least one direction bit and at least two register bits;

a processor that communicates with the bit alterable memory through a transmission path; and

an antennae coupled to the transmission path.

18. The system of claim 17, wherein an interface determines the programming state of the plurality of cell colonies after a power loss using the direction bit and the register bits.

19. The system of claim 17, wherein a number of cells in each of the plurality of cell colonies is configurable.

20. A bit alterable memory comprising:

a plurality of cell colonies having at least one direction bit and at least two register bits; and

an interface to determine the programming state of the plurality of cell colonies after a power loss using the direction and the register bits.

21. The bit alterable memory of claim 20, wherein each of the plurality of cell colonies comprises a configurable number of cells.

22. The bit alterable memory of claim 20, wherein the interface determines whether, upon a read operation, the direction bit is at a first state or a second state wherein the plurality of cell colonies comprises at least a first memory cell colony and a second memory cell colony.

23. The bit alterable memory of claim 22, wherein if the interface determines that the direction bit is at the first state, designating that a first memory cell colony is valid.

24. The bit alterable memory of claim 22, wherein if the interface determines that the direction bit and one register bit is at the first state and at least one register bit is at the second state, designating that the programming operation is not complete.

25. The bit alterable memory of claim 22, wherein the interface determines that the direction bit is at the second state, designating that the second memory cell colony is valid.

26. The bit alterable memory of claim 22, wherein if the interface determines that the direction bit and one register bit are at the second state and at least one register bit is at the first state, designating that the programming operation is not complete.