Partitioned shared cache

• US 20070143546A1
• Filed: 12/21/2005
• Published: 06/21/2007
• Est. Priority Date: 12/21/2005
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Narad, Charles
• Application Number:
  US11/314,229
• Publication Number:
  US 20070143546A1
• Time in Patent Office: Days
• US Class Current: 711/130
• CPC Class Codes: G06F 12/084 with a shared cache

Abstract

Some of the embodiments discussed herein may utilize partitions within a shared cache in various computing environments. In an embodiment, data shared between two memory accessing agents may be stored in a shared partition of the shared cache. Additionally, data accessed by one of the memory accessing agents may be stored in one or more private partitions of the shared cache.

Claims

1. An apparatus comprising:

a first memory accessing agent coupled to a shared cache;

a second memory accessing agent coupled to the shared cache, the second memory accessing agent comprising a plurality of processor cores; and

the shared cache comprising;

a shared partition to store data that is shared between the first memory accessing agent and the second memory accessing agent; and

at least one private partition to store data that is accessed by one or more of the plurality of processor cores.

2. The apparatus of claim 1, further comprising a cache controller to:

perform a first set of cache policies on a first partition of the shared cache for a memory access request by the first memory accessing agent; and

perform a second set of cache policies on one or more of the first partition and a second partition of the shared cache for a memory access request by the second memory accessing agent.

3. The apparatus of claim 2, wherein the first set of cache policies is a subset of the second set of cache policies.

4. The apparatus of claim 1, wherein at least one of the first memory accessing agent or the second memory accessing agent identifies a partition in the shared cache to which a memory access request is directed.

5. The apparatus of claim 1, wherein at least one of the first memory accessing agent or the second memory accessing agent identifies a cache policy that is applied to a memory transaction directed to the shared cache.

6. The apparatus of claim 1, wherein one or more of the plurality of processor cores perform a partial-write merge in one or more private partitions of the shared cache.

7. The apparatus of claim 1, further comprising one or more caches that have a lower level than the shared cache, wherein the one or more caches snoop one or more memory transactions directed to the shared partition.

8. The apparatus of claim 1, wherein the shared cache is one of a level 2 cache, a cache with a higher level than 2, or a last level cache.

9. The apparatus of claim 1, wherein the first agent comprises one or more processors.

10. The apparatus of claim 9, wherein at least one of the one or more processors comprise a level 1 cache.

11. The apparatus of claim 9, wherein at least one of the one or more processors comprises a plurality of caches in a multiple level hierarchy.

12. The apparatus of claim 1, wherein one or more of the plurality of processor cores comprise a level 1 cache.

13. The apparatus of claim 1, wherein at least one of the plurality of processor cores comprises a plurality of caches in a multiple level hierarchy.

14. The apparatus of claim 1, further comprising at least one private partition to store data that is accessed by the first memory accessing agent.

15. The apparatus of claim 1, wherein the first agent comprises at least one processor that comprises a plurality of processor cores.

16. The apparatus of claim 1, wherein the plurality of processor cores are on a same integrated circuit die.

17. The apparatus of claim 1, wherein the first agent comprises one or more processor cores and wherein the first memory accessing agent and the second memory accessing agent are on a same integrated circuit die.

18. A method comprising:

storing data that is shared between a first memory accessing agent and a second memory accessing agent in a shared partition of a shared cache, the second memory accessing agent comprising a plurality of processor cores; and

storing data that is accessed by one or more of the plurality of processor cores in at least one private partition of the shared cache.

19. The method of claim 18, further comprising storing data that is accessed by the first memory accessing agent in one or more private partitions of the shared partition.

20. The method of claim 18, further comprising identifying a cache partition in the shared cache to which a memory access request is directed.

21. The method of claim 18, further comprising:

performing a first set of cache policies on a first partition of the shared cache for a memory access request by the first memory accessing agent; and

performing a second set of cache policies on one or more of the first partition or a second partition of the shared cache for a memory access request by the second memory accessing agent.

22. The method of claim 18, further comprising identifying a cache policy that is applied to a memory transaction directed to the shared cache.

23. The method of claim 18, further comprising performing a partial-write merge in at least one private partition of the shared cache.

24. The method of claim 18, further comprising dynamically or statically adjusting a size of one or more partitions in the shared cache.

25. The method of claim 18, further comprising snooping one or more memory transactions directed to the shared partition of the shared cache.

26. A traffic management device comprising:

a switch fabric; and

an apparatus to process data communicated via the switch fabric comprising;

a cache controller to store the data in one of one or more shared partitions and one or more private partitions of a shared cache in response to a memory access request;

a first memory accessing agent and a second memory accessing agent to send the memory access request, the second memory accessing agent comprising a plurality of processor cores;

at least one of the one or more shared partitions to store data that is shared between the first memory accessing agent and the second memory accessing agent; and

at least one of the one or more private partitions to store data that is accessed by one or more of the plurality of processor cores.

27. The traffic management device of claim 26, wherein the switch fabric conforms to one or more of common switch interface (CSIX), advanced switching interconnect (ASI), HyperTransport, Infiniband, peripheral component interconnect (PCI), PCI Express (PCI-e), Ethernet, Packet-Over-SONET (synchronous optical network), or Universal Test and Operations PHY (physical) Interface for ATM (UTOPIA).

28. The traffic management device of claim 26, wherein the cache controller performs:

a first set of cache policies on a first partition of the shared cache for a memory access request by the first memory accessing agent; and

a second set of cache policies on one or more of the first partition and a second partition of the shared cache for a memory access request by the second memory accessing agent.

29. The traffic management device of claim 26, wherein the first memory accessing agent comprises at least one processor that comprises a plurality of processor cores.

30. The traffic management device of claim 26, further comprising at least one private partition to store data that is accessed by the first memory accessing agent.