Trench polysilicon diode

• US 20070145411A1
• Filed: 12/28/2005
• Published: 06/28/2007
• Est. Priority Date: 12/28/2005
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Pattanayak, Deva, Terrill, Kyle, Chen, Qufei, Xu, Robert
• Granted Patent: US 7,544,545 B2
• Time in Patent Office: Days
• US Class Current: 257/173
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0814 Diodes only
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/66106 Zener diodes
• CPC Class Codes: H01L 29/66136 PN junction diodes
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/866 Zener diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Embodiments of the present invention include a method of manufacturing a trench polysilicon diode. The method includes forming a N− (P−) type epitaxial region on a N+ (P+) type substrate and forming a trench in the N− (P−) type epitaxial region. The method further includes forming a insulating layer in the trench and filling the trench with polysilicon forming a top surface of the trench. The method further includes forming P+ (N+) type doped polysilicon region and N+ (P+) type doped polysilicon region in the trench and forming a diode in the trench wherein a portion of the diode is lower than the top surface of the trench.

Claims

1. A method of manufacturing a vertical trench polysilicon diode comprising:

forming a N−

(P−

) type epitaxial region on N+ (P+) type substrate;

forming a trench in said epitaxial region;

forming an insulating layer in said trench;

filling said trench with polysilicon forming a top surface of said trench;

implanting a P+ (N+) type dopant, forming a P+ (N+) type region of said polysilicon in said trench;

implanting a N+ (P+) type dopant, forming a N+ (P+) type region of said polysilicon in said trench;

forming a polysilicon diode in said trench wherein a portion of said diode is lower than said top surface of said trench.

2. The method as described in claim 1 wherein said insulating layer comprises an oxide.

3. The method as described in claim 1 wherein said insulating layer in said trench has a breakdown voltage rating greater than a drain-source breakdown voltage of trench MOSFET transistor for excellent isolation between them.

4. The method as described in claim 1 wherein said insulating layer is of a few thousand angstroms in thickness and said insulating layer thickness in said trench is depend on the its breakdown voltage requirement.

5. The method as described in claim 1 wherein formation of said diode is prior to the formation of a MOSFET trench of said transistor.

6. The method as described in claim 1 wherein said diode is a Zener diode.

7. The method as described in claim 6 wherein said Zener diode is used for electrostatic discharge protection.

8. The method as described in claim 1 wherein said Zener diode is used for a clamping function.

9. The method as described in claim 1 wherein said diode is a trench diode and is used for temperature sensing.

10. The method as described in claim 1 wherein said N+ (P+) type doped polysilicon in said trench is used as a resistor.

11. A trench polysilicon diode comprising electrostatic discharge protection comprising:

a N+ (P+) type substrate;

a N−

(P−

) type epitaxial region over said substrate;

a trench formed in said N−

(P−

) type epitaxial region, said trench comprising a top surface;

an insulating layer lining said trench;

a polysilicon filling said trench forming a top surface of said trench;

a P+ (N+) type doping polysilicon in said trench and formed by a P+ (N+) type ESD implant;

a N+ (P+) type doping polysilicon in said trench and formed by a N+ (P+) type source implant;

a diode formed in said trench such that a portion of said diode is formed below said top surface of said trench.

12. The trench polysilicon diode as described in claim 11 wherein said insulating layer comprises an oxide.

13. The trench polysilicon diode as described in claim 11 wherein said insulating layer in said trench has a breakdown voltage rating greater than a drain-source breakdown voltage of trench MOSFET transistor for excellent isolation between them.

14. The trench polysilicon diode as described in claim 11 wherein said insulating layer is of a few thousand angstroms in thickness and said insulating layer thickness in said trench is depend on the its breakdown voltage requirement.

15. The trench polysilicon diode as described in claim 11 wherein said diode is formed prior to the formation of a MOSFET trench of said transistor.

16. The trench polysilicon diode as described in claim 11 wherein said diode is a Zener diode.

17. The trench polysilicon diode as described in claim 16 wherein said Zener diode is used for electrostatic discharge protection.

18. The trench polysilicon diode as described in claim 16 wherein said Zener diode is used for a clamping function.

19. The trench polysilicon diode as described in claim 11 wherein said diode is a trench diode and is used for temperature sensing.

20. The trench polysilicon diode as described in claim 11 wherein said N+ (P+) type doped polysilicon in said trench is used as a resistor.

21. A method of manufacturing a trench polysilicon diode comprising:

forming a trench in a N−

(P−

) type epitaxial region on a N+ (P+) type substrate;

forming an insulating layer in said trench wherein said insulating layer lines said trench;

filling said trench with a polysilicon forming a top surface of said trench;

forming a diode in said body region wherein a portion of said diode is lower than said top surface of said trench.

22. The method as described in claim 21 further comprising:

forming a plurality of Zener diodes in said N−

(P−

) type epitaxial region and coupling said plurality of Zener diodes in parallel to protect said transistor from electrostatic discharge.

23. The method as described in claim 21 wherein said insulating layer comprises an oxide.

24. The method as described in claim 21 wherein said insulating layer in said trench has a breakdown voltage rating greater than a drain-source breakdown voltage of trench MOSFET transistor for excellent isolation between them.

25. The method as described in claim 21 wherein said insulating layer is of a few thousand angstroms in thickness and said insulating layer thickness in said trench is depend on the its breakdown voltage requirement.

26. The method as described in claim 21 wherein formation of said diode occurs prior to the formation of a MOSFET trench of said transistor.

27. The method as described in claim 21 wherein said diode is a Zener diode.

28. The method as described in claim 27 wherein said Zener diode is used for electrostatic discharge protection.

29. The method as described in claim 27 wherein said Zener diode is used for a clamping function.

30. The method as described in claim 21 wherein said diode is a trench diode and is used for temperature sensing.

31. The method as described in claim 21 wherein said N+ (P+) type doped polysilicon in said trench is used as a resistor.

32. A temperature sensor comprising:

a first trench polysilicon diode electrically coupled to a first pin and a second pin wherein a portion of said first trench polysilicon diode is under the surface a N−

(P−

) type epitaxial region;

a second trench polysilicon diode coupled to said first pin and said second pin wherein said first trench polysilicon diode and said second trench polysilicon diode are coupled in anti-parallel and wherein a temperature can be determined by a voltage measured between said first pin and said second pin and wherein a portion of said second trench polysilicon diode is under said surface said N−

(P−

) type epitaxial region.

33. The temperature sensor as described in claim 32 wherein said first and second trench diodes are trench polysilicon diodes.

34. The temperature sensor as described in claim 32 further comprising a look-up table comprising a plurality of voltages and corresponding temperature values.

35. The temperature sensor as described in claim 32 wherein said first and second diodes comprise a P+ type polysilicon region and an N+ type polysilicon region.