SEMICONDUCTOR DEVICE

• US 20070145434A1
• Filed: 12/26/2006
• Published: 06/28/2007
• Est. Priority Date: 12/28/2005
• Status: Abandoned Application

• Current Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Kim, Jung Ho
• Application Number:
  US11/616,283
• Publication Number:
  US 20070145434A1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Embodiments relate to a method for manufacturing a semiconductor substrate. According to embodiments, a gate oxide layer may be formed on a semiconductor substrate. Also, a well region may be formed in the semiconductor substrate including the gate oxide layer. Then, after forming a gate electrode on the semiconductor substrate, a liner layer may be formed on the semiconductor substrate. Next, the semiconductor substrate including the liner layer may be annealed to form an annealed liner layer. Finally, an interlayer insulation layer may be formed on the annealed liner layer.

Claims

1. A device comprising:

a semiconductor substrate including a device isolation layer;

a well region formed in the semiconductor substrate;

a gate oxide layer formed over the semiconductor substrate;

a gate electrode formed over the gate oxide layer; and

an annealed liner layer formed over the gate oxide layer and the gate electrode.

2. The device of claim 1, further comprising an interlayer insulation layer formed over the annealed liner layer.

3. The device of claim 1, wherein the annealed liner layer is formed on a sidewall of the gate electrode.

4. The device of claim 1, wherein the semiconductor substrate comprises a high and a low voltage device region, and the annealed liner layer is formed in the high voltage device region of the semiconductor substrate.

5. The device of claim 1, wherein the annealed liner layer is formed by annealing one of a preferential metal deposition layer based layer, a middle temperature oxide based layer, and a high temperature oxide based layer.

6. The device of claim 1, were the gate oxide layer comprises an ion implanted oxide layer formed over the well region and an oxide layer formed over a non-well region.

7. A method comprising:

forming a gate oxide layer over a semiconductor substrate;

forming a well region in the semiconductor substrate including the gate oxide layer;

forming a gate electrode over the semiconductor substrate;

forming a liner layer over the semiconductor substrate; and

annealing the semiconductor substrate including the liner layer to form an annealed liner layer.

8. The method of claim 7, further comprising forming an interlayer insulation layer on the annealed liner layer.

9. The method of claim 7, where the gate oxide layer comprises an ion implanted oxide layer formed over the well region in the semiconductor substrate, and an oxide layer formed over remaining portions of the semiconductor substrate.

10. The method of claim 7, wherein the gate electrode is formed over a portion of the ion implanted oxide layer and a portion of the oxide layer.

11. The method of claim 7, wherein the annealing is performed at a temperature range of 600˜

1000°

C. under a N₂ or H₂ atmosphere.

12. The method of claim 7, wherein forming the liner layer comprises depositing at least one of a preferential metal deposition layer based material, a middle temperature oxide based material, and a high temperature oxide based material.

13. The method of claim 7, further comprising forming a device isolation layer in the semiconductor substrate to divide a high voltage device region from a low voltage device region before the forming of the gate oxide layer.

14. The method of claim 13, wherein the liner layer is formed in the high voltage device region of the semiconductor substrate.

15. The method of claim 7, wherein the interlayer insulation layer comprises at least one of a boro-phosphosilicate glass, a phosphosilicate glass and an undoped silicate glass.

16. A device, comprising:

a semiconductor substrate having a well region formed therein;

an ion implanted oxide layer over at least a portion of the well region; and

an annealed linear layer over at least a portion of the ion implanted oxide layer.

17. The device of claim 16, further comprising:

a gate electrode formed over a portion of the ion implanted oxide layer and a portion of an oxide layer;

in interlayer insulation layer formed over the annealed linear layer, where the annealed linear layer is formed over the gate electrode.

18. The device of claim 17, wherein the annealed linear layer is formed on a side wall of the to electric.

19. The device of claim 17, wherein the oxide layer and the ion implanted oxide layer form a single gate oxide layer over the semiconductor substrate.

20. The device of claim 17, further comprising a device isolation layer configured to divide the semiconductor substrate into a high voltage device region and a low voltage device region, wherein the liner layer is formed in the high voltage device region.