Semiconductor device and method of manufacturing the same

• US 20070145470A1
• Filed: 02/22/2007
• Published: 06/28/2007
• Est. Priority Date: 05/26/2003
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ozawa, Yoshio
• Application Number:
  US11/709,161
• Publication Number:
  US 20070145470A1
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film provided on the semiconductor substrate, a floating gate electrode provided on the tunnel insulating film, the width of the floating gate electrode changing in the height direction of the non-volatile memory cell in channel width or length direction there, and being thinnest between a region above the bottom surface of the floating gate electrode and a region below the upper surface thereof, a control gate electrode above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

Claims

1-9. -9. (canceled)

10. A semiconductor device comprising:

a semiconductor substrate; and

a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising;

a tunnel insulating film provided on the semiconductor substrate;

a floating gate electrode provided on the tunnel insulating film;

a control gate electrode above the floating gate electrode; and

an interelectrode insulating film provided between the control gate electrode and the floating gate electrode, the interelectrode insulating film including a first dielectric region and a second dielectric region having permittivity lower than the first dielectric region, the second dielectric region being provided on an edge of the first dielectric region in a channel length direction of the non-volatile memory cell.

11-20. -20. (canceled)

21. A semiconductor device comprising:

a semiconductor substrate; and

a non-volatile memory cell provided on the semiconductor substrate,

the non-volatile memory cell comprising;

a tunnel insulating film provided on the semiconductor substrate;

a floating gate electrode provided on the tunnel insulating film, the width of the floating gate electrode changing in a height direction of the non-volatile memory cell in a channel width direction, and being thinnest between a region above a bottom surface of the floating gate electrode and a region below an upper surface thereof;

a control gate electrode above the floating gate electrode; and

an interelectrode insulating film provided between the control gate electrode and the floating gate electrode;

wherein a distribution of a width of the floating gate electrode in a height direction of the non-volatile memory cell in the channel width direction shows a maximum width at a first position away from the bottom surface of the floating gate electrode with a predetermined distance and a minimum width at a second position above a first position in the channel width direction,

the isolation film includes a top surface which is higher than that of the floating gate electrode in the channel width direction,

the interelectrode insulating film covers a top side portion of the floating gate electrodes in the channel width direction, and

an area of the tunnel insulating film facing the floating gate electrode is smaller than an area of the interelectrode insulating film facing the floating gate electrode.

22. A semiconductor device comprising:

a semiconductor substrate; and

a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising;

a tunnel insulating film provided on the semiconductor substrate;

a floating gate electrode provided on the tunnel insulating film, the width of the floating gate electrode changing in a height direction of the non-volatile memory cell in a channel width direction, and being thinnest at an approximately intermediate position between a region above the bottom surface of the floating gate electrode and a region below the upper surface thereof;

a control gate electrode above the floating gate electrode; and

an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

wherein a distribution of the width of the floating gate electrode in a height direction of the non-volatile memory cell in the channel width direction shows a maximum width at a first position away from the bottom surface of the floating gate electrode with a predetermined distance and a minimum width at a second position above the first position in the channel width direction,

the isolation film includes a top surface which is higher than that of the floating gate electrode in the channel width direction,

the interelectrode insulating film covers a top side portion of the floating gate electrode in the channel width direction and

an area of the tunnel insulating film facing the floating gate electrode is smaller than an area of the interelectrode insulating film facing the floating gate electrode.