Multigate device with recessed strain regions

• US 20070145487A1
• Filed: 12/27/2005
• Published: 06/28/2007
• Est. Priority Date: 12/27/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Intel Corporation
• Inventors: Kavalieros, Jack, Datta, Suman, Chau, Robert, Doyle, Brian, Brask, Justin
• Granted Patent: US 7,525,160 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Embodiments of the invention provide a device with a multiple gates. Stress material within recesses of a device body metal gate may cause a stress in channel regions of the device, thereby improving performance of the device.

Claims

1. A semiconductor device, comprising:

a substrate comprising a semiconductor material, the semiconductor material having a first crystal lattice with a first lattice structure and a first lattice spacing;

a body region of the substrate, the body region having a top surface and side walls, the side walls being separated by a width and extending for a length;

a gate electrode on a portion of the top surface and side walls of the body region;

a source recess and a drain recess in the body region on either side of the gate electrode; and

a stress material in the source and drain recesses, the stress material comprising a second material with a second crystal lattice with a second lattice structure substantially the same as the first lattice structure and a second lattice spacing different than the first lattice spacing.

2. The device of claim 1, further comprising channel regions in the substrate between the source and the drain under the gate electrode and adjacent the top surface and side walls of the body region.

3. The device of claim 1, wherein the substrate is not a semiconductor-on-insulator substrate.

4. The device of claim 1, further comprising:

front and back shallow trench isolation regions, with the length of the body region being between the front and back shallow trench isolation regions;

side shallow trench isolation regions in the substrate on either side of the side walls of the body region; and

wherein the shallow trench isolation regions have a depth.

5. The device of claim 4, wherein the top surface of the body region, under the gate electrode, is a height above the side shallow trench isolation regions.

6. The device of claim 5, wherein the height of the body region is at least about twice the width of the body region.

7. The device of claim 5, wherein the depth of the shallow trench isolation regions is at least about twice the height of the body region.

8. The device of claim 7, wherein the height of the body region is at least about twice the width of the body region.

9. The device of claim 1, wherein the source and drain recesses are recessed into the top surface of the body region as well as into the side walls of the body region.

10. The device of claim 9, wherein the source and the drain comprise the second material and the second material extends vertically beyond the top surface and horizontally beyond the side walls of the body region at the source and at the drain.

11. The device of claim 10, wherein the second lattice spacing is larger than the first lattice spacing.

12. The device of claim 10, wherein the second lattice spacing is smaller than the first lattice spacing.

13. A semiconductor device, comprising:

a substrate comprising a semiconductor material with a first lattice with a first lattice structure and a first lattice spacing, the substrate not being a semiconductor-on-insulator substrate;

front, back, and side shallow trench isolation regions in the substrate, the shallow trench isolation regions having a depth;

a body region of the substrate, at least a portion of the body region extending a height above the shallow trench isolation regions, the body region having a length between the front and back shallow trench isolation regions and a width between the side shallow trench isolation regions;

a gate electrode on a top surface and side walls of the body region;

channel regions in the body region under the gate electrode;

source/drain recesses on either side of the gate electrode, the source/drain recesses including recesses in the top surface and the side walls of the body region; and

a second material in the source/drain recesses with a second lattice structure substantially the same as the first lattice structure and a second lattice spacing different than the first lattice spacing.

14. The device of claim 13, wherein the width is between about 20 nanometers and about 40 nanometers and the height is between about 1.8 times the width and about 2.2 times the width.

15. The device of claim 14, wherein the height of the body region is between about 400 angstroms and about 600 angstroms and the depth of the shallow trench isolation regions is between about 900 and about 1100 angstroms.

16. The device of claim 15, wherein the second material in the source/drain recesses extends beyond the top surface and the side walls of the body region at the source and at the drain.

17. A method, comprising:

removing portions of a substrate comprising a semiconductor material with a first lattice with a first lattice structure and a first lattice spacing to form a fin with a top surface and side walls, the fin having a width between the side walls;

forming a gate electrode on the top and sidewalls of the fin, channel regions being beneath the gate electrode adjacent the top and the sidewalls;

removing portions of the fin on either side of the gate electrode to result in source/drain recesses extending into the top and sidewalls; and

forming a second material with a second lattice a second lattice spacing different than the first lattice spacing in the source/drain recesses.

18. The method of claim 17, wherein the substrate is not a semiconductor-on-insulator substrate.

19. The method of claim 18, further comprising forming side shallow trench isolation regions in the substrate on either side of the side walls of the body region, the body region having a height above the shallow trench isolation regions, and the shallow trench isolation regions having a depth.

20. The method of claim 19, wherein the depth of the shallow trench isolation regions is at least about twice the height of the body region.

21. The device of claim 20, wherein the height of the body region is at least about twice the width of the body region.