Time interval trimmed differential capacitance sensor

• US 20070146019A1
• Filed: 12/22/2005
• Published: 06/28/2007
• Est. Priority Date: 12/22/2005
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Foote, Steven
• Granted Patent: US 7,368,923 B2
• Time in Patent Office: Days
• US Class Current: 327/100
• CPC Class Codes: G01D 5/24 by varying capacitance

Abstract

An apparatus and method for operation of a differential capacitance transducer, including generating substantially opposing polarity excitation drive signals by operation of a pair of drive signal generators, applying the excitation drive signals to a pair of sense capacitors of a differential capacitance sensor, sensing a differential capacitance at a common junction between the pair of sense capacitors; and individually controlling the drive signal generators for trimming a null bias of the sense capacitor pair at the common junction.

Claims

1. :

A detector drive circuit for operation of a differential capacitance transducer, the circuit comprising;

a pair of sense capacitors;

a pair of drive signal generators that are structured to apply respective substantially opposing polarity excitation drive signals to the respective sense capacitors; and

a null bias trim circuit coupled for individually controlling the respective drive signal generators.

2. :

The circuit of claim 1, further comprising;

a transimpedence amplifier coupled to a common junction between the pair of sense capacitors;

a synchronous demodulator coupled to an output of the transimpedence amplifier; and

a filter buffer coupled to an output of the synchronous demodulator.

3. :

The circuit of claim 2, further comprising a pair of switches coupled between the null bias trim circuit and the respective drive signal generators and being operated individually by the null bias trim circuit.

4. :

The circuit of claim 3, further comprising a digital controller comprising the null bias trim circuit.

5. :

The circuit of claim 4, further comprising a system clock oscillator, each of the respective excitation drive signals having an excitation frequency that is a fraction of a clock frequency of the system clock oscillator.

6. :

The circuit of claim 5 wherein the respective excitation drive signals have different first and second time widths.

7. :

The circuit of claim 1, further comprising a switch between the transimpedence amplifier and the synchronous demodulator; and

a scale factor trim circuit coupled for controlling the switch.

8. :

The circuit of claim 7, further comprising a temperature sensor coupled to output a temperature signal representative of system temperature to the scale factor trim circuit, the scale factor trim circuit being further structured for variable control of the gate switch as a function of the temperature signal.

9. :

The circuit of claim 1, further comprising a temperature sensor coupled to output a temperature signal representative of system temperature to the null bias trim circuit, the null bias trim circuit being further structured for variable control of the respective drive signal generators as a function of the temperature signal.

10. :

A detector drive circuit for operation of a differential capacitance transducer, the circuit comprising;

a high frequency system clock oscillator;

a differential capacitance sensor having first and second sense capacitors that are coupled to a common junction therebetween;

a drive circuit having first and second drive signal generators that are sourced as a division of the system clock oscillator and are structured to generate respective first and second substantially opposing polarity excitation drive signals, the first and second drive signal generators being coupled to apply the respective first and second excitation drive signals to the respective sense capacitors of the differential capacitance sensor;

first and second switches coupled for controlling the respective first and second drive signal generators;

a programmable null bias trim circuit coupled for individually controlling the first and second switches;

a transimpedence amplifier coupled to the common junction between the sense capacitors;

a synchronous demodulator coupled to the transimpedence amplifier; and

a filter buffer coupled to the synchronous demodulator.

11. :

The circuit of claim 10 wherein the null bias trim circuit is further structured for controlling the first and second switches to adjust drive excitation time widths of the respective individual first and second drive signal generators in time increments of the system clock oscillator.

12. :

The circuit of claim 11 wherein the null bias trim circuit is further structured to individually control the first of the signal generator to generate the first excitation drive signal having a first width, and is further structured to individually control the second signal generators to generate the second excitation drive signal having a second width that is different from the first width by one or more clock increments.

13. :

The circuit of claim 10, further comprising a gate switch between the transimpedence amplifier and the synchronous demodulator, and a programmable scale factor trim circuit coupled for controlling the gate switch.

14. :

The circuit of claim 13 wherein at least one of the programmable null bias trim circuit and the programmable scale factor trim circuit is further coupled for receiving a temperature signal representative of system temperature, and at least one of the programmable null bias trim circuit and the programmable scale factor trim circuit is further structured for variable control of the drive signal generators and the gate switch, respectively, as a function of the temperature signal.

15. :

A method for operation of a differential capacitance transducer, the method comprising;

generating first and second substantially opposing polarity excitation drive signals by operation of respective first and second drive signal generators;

applying the first and second excitation drive signals to respective first and second sense capacitors of a differential capacitance sensor;

sensing a differential capacitance at a common junction between the first and second sense capacitors; and

individually controlling the respective first and second drive signal generators for trimming a null bias of the first and second sense capacitors at the common junction.

16. :

The method of claim 15 wherein generating first and second substantially opposing polarity excitation drive signals further comprises sourcing the respective first and second drive signal generators as the division of a high frequency system clock oscillator.

17. :

The method of claim 16 wherein individually controlling the respective first and second drive signal generators further comprises individually adjusting drive excitation time widths of the respective first and second drive signal generators in time increments of the system clock oscillator.

18. :

The method of claim 17, further comprising controlling a gate switch for passing only portion of a differential capacitance signal received at the common junction, the portion of the signal passed being proportional to a duty cycle of the switch.

19. :

The method of claim 17, further comprising alternating the excitation drive signals between different time increments of the system clock oscillator to obtain a higher resolution trimming function.

20. :

The method of claim 19 wherein individually controlling the respective first and second drive signal generators further comprises individually controlling first and second switches coupled for individually controlling the respective first and second drive signal generators.