Alternate sensing techniques for non-volatile memories

• US 20070147113A1
• Filed: 12/28/2005
• Published: 06/28/2007
• Est. Priority Date: 12/28/2005
• Status: Active Grant

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Mokhlesi, Nima, Lutze, Jeffrey
• Granted Patent: US 7,349,264 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.

Claims

1. A method of operating an array of memory cells connected along word lines and bit lines, comprising:

selecting a multi-state memory cell for a sensing operation;

discharging the sensing node of the selected memory cell to ground through the bit line along which it is connected;

subsequent to discharging the sensing node of the selected memory cell;

applying a first voltage level to the source of the selected memory cell; and

applying a second voltage level to the word line along which the selected memory cell is connected, wherein the first and second voltage levels are independent of the data content stored within the selected cell;

subsequent to applying the first and second voltage levels, allowing a corresponding voltage to develop upon the bit line along which the selected memory cell is connected;

performing a first sensing operation, including comparing the voltage developed at the sensing node of the selected memory cell to a first plurality of reference values in order to determine whether the data content of the selected memory cell corresponds to one of a first subset of said multi-states;

subsequent to performing the first sensing operation, applying a third voltage level to the word line along which the selected memory cell is connected, wherein the second and third voltage levels are distinct;

subsequent to applying the third voltage level, allowing a corresponding voltage to develop upon the bit line along which the selected memory cell is connected; and

performing a second sensing operation, including comparing the voltage developed at the sensing node of the selected memory cell to a second plurality of reference values in order to determine whether the data content of the selected memory cell corresponds to one of a second subset of said multi-states, wherein the first and second subsets of said multi-states are distinct and each contain a plurality of states.

2. The method of claim 1, wherein the first and second plurality of reference values are the same.

3. The method of claim 1, wherein the first and second subsets of said multi-states are non-overlapping.

4. The method of claim 1, wherein the combination of the first and second subsets of said multi-states contain less than all of said multi-states.

5. The method of claim 1, further comprising:

subsequent to the first sensing operation and prior to the second sensing operation, discharging the sensing node of the selected memory cell to ground through the bit line along which it is connected.

6. The method of claim 1, wherein the sensing node corresponds to the bit line along which the selected memory cell is connected.

7. The method of claim 1, wherein the sensing node is an intermediate node for the bit line along which the selected memory cell is connected.

8. The method of claim 1, wherein said selected memory cell is one of a plurality of memory cells selected for a concurrent sensing operation.

9. The method of claim 8, wherein said plurality of memory cells selected for a concurrent sensing operation are formed along said word line.

10. The method of claim 1, wherein said array has a NAND architecture.

11. The method of claim 10, wherein said array has an all bit line architecture.

12. The method of claim 1, wherein said sensing operations are performed during the verification phase of a write operation.

13. The method of claim 1, wherein said sensing operations are performed during a read operation.

14. The method of claim 1, wherein the voltage developed along the bit line in the first and second sensing operations is respectively compared to at least some of the first and second pluralities of reference values sequentially.

15. The method of claim 1, wherein the voltage developed along the bit line in the first and second sensing operations is respectively compared to at least some of the first and second pluralities of reference values concurrently.

16. A method of concurrently determining the state of a plurality of multi-state memory cells from a memory array, wherein said plurality of memory cells are connected along a common word line, have sources connected to a common source line, and are formed along distinct bit lines, the method comprising:

discharging the memory cells to ground through the corresponding bit lines;

subsequently applying a first voltage level to the common source line;

subsequently applying a second voltage level to the word line;

in response to applying the second voltage level to the word line, determining whether the data content of each of the memory cells corresponds to one of a first subset of said multi-states;

subsequently applying a third voltage level to the word line, wherein the third voltage level differs from the second voltage level; and

in response to applying the third voltage level to the word line, determining whether the data content of each of the memory cells corresponds to one of a second subset of said multi-states, wherein the first and second subsets of said multi-states are distinct and each contain a plurality of states.

17. The method of claim 16, wherein determining whether the data content of each of the memory cells corresponds to one of a first or second subset of said multi-states includes:

allowing a voltage to develop upon each of the corresponding bit lines; and

comparing the voltages developed along the bit lines to a plurality of reference values in order to determine the data content of the memory cells.

18. The method of claim 16, wherein the first and second subsets of said multi-states are non-overlapping.

19. The method of claim 16, wherein the combination of the first and second subsets of said multi-states contain less than all of said multi-states.

20. The method of claim 16, wherein said array has a NAND architecture.

21. The method of claim 20, wherein said array has an all bit line architecture.

22. The method of claim 16, wherein determining whether the data content of each of the memory cells corresponds to one of a first subset and determining whether the data content of each of the memory cells corresponds to one of a second subset are performed during the verification phase of a write operation.

23. The method of claim 16, wherein determining whether the data content of each of the memory cells corresponds to one of a first subset and determining whether the data content of each of the memory cells corresponds to one of a second subset are performed during a read operation.

24. A method of writing multi-state data concurrently to a plurality of multi-state memory cells from a memory array, wherein said plurality of memory cells are connected along a common word line, have sources connected to a common source line, and are formed along distinct bit lines, the method comprising:

applying a common programming pulse to the word line while controlling the amount of charge injected into each of said memory cell on a bit line by bit line basis based on the corresponding target state of each of said memory cells; and

subsequently performing a verify operation, comprising;

discharging the memory cells to ground through the corresponding bit lines;

subsequently applying a first voltage level to the common source line;

subsequently applying a second voltage level to the word line;

in response to applying the second voltage level to the word line, determining whether the data content of each of the memory cells corresponds to one of a first subset of said multi-states;

subsequently applying a third voltage level to the word line, wherein the third voltage level differs from the second voltage level; and

in response to applying the third voltage level to the word line, determining whether the data content of each of the memory cells corresponds to one of a second subset of said multi-states, wherein the first and second subsets of said multi-states are distinct and each contain a plurality of states.

25. The method of claim 24, wherein determining whether the data content of each of the memory cells corresponds to one of a first or second subset of said multi-states includes:

allowing a voltage to develop upon each of the corresponding bit lines; and

comparing the voltages developed along the bit lines to a plurality of reference values in order to determine the data content of the memory cells.

26. The method of claim 24, wherein said controlling the amount of charge injected into each of said memory cell on a bit line by bit line basis based on the corresponding target state of each of said memory cells includes setting a voltage level on said bit lines on a bit line by bit line basis based on said corresponding target state of each of said memory cells.

27. The method of claim 24, wherein said controlling the amount of charge injected into each of said memory cell on a bit line by bit line basis based on the corresponding target state of each of said memory cells includes setting a current limit on said bit lines on a bit line by bit line basis based on said corresponding target state of each of said memory cells.