Page buffer and related reading method

• US 20070147120A1
• Filed: 08/31/2006
• Published: 06/28/2007
• Est. Priority Date: 12/28/2005
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Tae-Young
• Application Number:
  US11/513,162
• Publication Number:
  US 20070147120A1
• Time in Patent Office: Days
• US Class Current: 365/185.170
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches

Abstract

A page buffer and a reading method comprising a unitary operation adapted to execute either a normal read operation or a copyback read operation using a page buffer are disclosed. The unitary operation comprises initializing a latch to store a first logic value; sensing a voltage level corresponding to a programming state of a selected memory cell; and selectively storing a second logic value in the latch in response to the sensed voltage level, wherein the page buffer enters a programming operation mode when the second logic value is stored in the latch.

Claims

1. A reading method comprising:

a unitary operation, the unitary operation adapted to execute either a normal read operation or a copyback read operation using a page buffer, the unitary operation comprising;

initializing a latch to store a first logic value;

sensing a voltage level corresponding to a programming state of a selected memory cell; and

,

selectively storing a second logic value in the latch in response to the sensed voltage level,

wherein the page buffer enters a programming operation mode when the second logic value is stored in the latch.

2. The method of claim 1, wherein selectively storing the second logic value in the latch in response to the sensed voltage level comprises storing the second logic value in the latch if the sensed voltage level is a first voltage level, wherein the first voltage level indicates that the selected memory cell is programmed.

3. The method of claim 1, wherein selectively storing a second logic value in the latch in response to the sensed voltage level comprises continuing to store the first logic value in the latch if the sensed voltage level is a first voltage level, wherein the first voltage level indicates that the selected memory cell is erased.

4. The method of claim 1, wherein, in each of the normal read operation and the copyback read operation, selectively storing the second logic value in the latch in response to the sensed voltage level comprises selectively storing the second logic value in the latch in response to the sensed voltage level using a first electrical path of the page buffer.

5. The method of claim 1, wherein the latch stores the same logic value at corresponding stages of the normal read operation and a corresponding copyback read operation.

6. The method of claim 1, wherein the page buffer enters a program-inhibit operation mode when the first logic value is stored in the latch.

7. A method for performing a copyback read operation in a page buffer comprising:

initializing a latch to store a first logic value;

sensing a voltage level corresponding to a programming state of a selected memory cell; and

,

selectively storing a second logic value in the latch in response to the sensed voltage level,

wherein the page buffer enters a programming operation mode when the second logic value is stored in the latch.

8. The method of claim 7, wherein selectively storing the second logic value in the latch in response to the sensed voltage level comprises storing the second logic value in the latch if the sensed voltage level is a first voltage level, wherein the first voltage level indicates that the selected memory cell is programmed.

9. The method of claim 7, wherein selectively storing the second logic value in the latch in response to the sensed voltage level comprises continuing to store the first logic value in the latch if the sensed voltage level is a first voltage level, wherein the first voltage level indicates that the selected memory cell is erased.

10. The method of claim 7, wherein the page buffer enters a program-inhibit operation mode when the first logic value is stored in the latch.

11. A page buffer adapted to perform either a normal read operation or a copyback read operation using a unitary operation, the page buffer comprising:

a bitline select and bias unit adapted to select a bitline corresponding to a selected memory cell;

a precharge unit adapted to precharge the bitline; and

,

a sense and latch unit adapted to sense a level of a voltage apparent on the bitline and store a logic value in a latch in response to the sensed voltage level,

wherein the latch is initialized to store a first logic value during each of the normal read operation and the copyback read operation; and

,

wherein the value stored in the latch changes from the first logic value to a second logic value if the sensed voltage level indicates that the selected memory cell is programmed.

12. The page buffer of claim 11, wherein the page buffer enters a program-inhibit operation mode when the first logic value is stored in the latch.

13. The page buffer of claim 11, wherein the page buffer enters a programming operation mode when the second logic value is stored in the latch.

14. The page buffer of claim 11, wherein, in each of the normal read operation and the copyback read operation, the page buffer is adapted to store logic values in the latch using a first electrical path of the page buffer.

15. The page buffer of claim 11, wherein the latch stores the same logic value at corresponding stages of the normal read operation and a corresponding copyback read operation.

16. The page buffer of claim 11, wherein the sense and latch unit is adapted to continue storing the first logic value in the latch if the sensed voltage indicates that the selected memory cell is erased.