Method of fabricating a multi-cornered film

• US 20070148837A1
• Filed: 12/27/2005
• Published: 06/28/2007
• Est. Priority Date: 12/27/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Chau, Robert, Doyle, Brian, Brask, Justin
• Granted Patent: US 7,396,711 B2
• Time in Patent Office: Days
• US Class Current: 438/164
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

Embodiments of the present invention describe a method of forming a multi-cornered film. According to the embodiments of the present invention, a photoresist mask is formed on a hard mask film formed on a film. The hard mask film is then patterned in alignment with the photoresist mask to produce a hard mask. The width of the photoresist mask is then reduced to form a reduced width photoresist mask. A first portion of the film is then etched in alignment with the hard mask. The hard mask is then etched in alignment with the reduced width photoresist mask to form a reduced width hard mask. A second portion of the film is then etched in alignment with the reduced width hard mask.

Claims

1. A method of patterning a film comprising:

forming a photoresist mask having a first width on a hard mask film formed on a film;

patterning said hard mask film in alignment with said photoresist mask to produce a hard mask;

reducing the width of said photoresist mask to form a reduced width photoresist mask having a second width;

etching a first portion of said film in alignment with the hard mask;

etching said hard mask in alignment with said reduced width photoresist mask to form a reduced width hard mask; and

etching a second portion of said film in alignment with said reduced width hard mask.

2. The method of claims 1 wherein said first portion of said film is etched said first time after forming said reduced width photoresist mask.

3. The method of claim 1 wherein said first portion of said film is etched said first time prior to forming said reduced width photoresist mask.

4. The method of claim 1 further comprising reducing the width of said photoresist mask a second time to form a second reduced width photoresist mask;

etching said hard mask a second time in alignment with said second reduced width photoresist mask to form a second reduced width hard mask; and

etching a third portion of said film in alignment with said second reduced width hard mask.

5. The method of claim 1 wherein said etching of said first and second portions of said semiconductor film utilizes an anisotropic etching process.

6. The method of claim 1 wherein said photoresist mask width is reduced utilizing an O₂ plasma ashing.

7. The method of claim 1 wherein said film is a silicon film.

8. The method of claim 7 wherein said silicon film is etched utilizing a plasma etch process utilizing a gas chemistry comprising HBr/CL₂/O₂.

9. The method of claim 1 further comprising forming a dielectric layer and a gate electrode over said first portion and said second portion of said film and wherein said film is a semiconductor film.

10. A method of forming a multi-cornered nonplanar device comprising:

forming a photoresist mask having a first width on a hard mask film formed on a semiconductor film having a first thickness formed on an insulating substrate;

etching said hard mask film in alignment with said photoresist mask to form a hard mask having a first width, said hard mask covering a central portion of said semiconductor film and exposing a first and second portion of said semiconductor film on opposite sides of said hard mask;

reducing the width of said photoresist mask to produce a reduced width photoresist mask having a second width;

anisotropically etching said semiconductor film in alignment with said hard mask having said first width so that said first and second portion of said semiconductor film has a second thickness less than said first thickness;

etching said hard mask in alignment with said reduced width photoresist mask to form a reduced width hard mask having said second width, said reduced width hard mask exposing a third and fourth portion of said semiconductor film on opposite sides of said reduced width hard mask, wherein said third and fourth portions of said semiconductor film are part of said central portion;

anisotropically etching said third and fourth portions of said semiconductor film in alignment with said reduced width hard mask, wherein said second etch of said semiconductor film also etches said first and second portions of said semiconductor film to thereby form a semiconductor body having sidewalls and a top surface wherein the sidewalls have a stair step configuration;

forming a gate dielectric layer on the side and top surface of said semiconductor body; and

forming a gate electrode over said gate dielectric layer formed on said sidewalls and top surface of said semiconductor body.

11. The method of claim 10 wherein said semiconductor film is silicon.

12. The method of claim 10 wherein said hard mask is selected from the group consisting of silicon nitride and silicon oxynitride.

13. The method of claim 10 wherein said photoresist mask is reduced by a plasma ashing.

14. The method of claim 10 wherein said semiconductor film is silicon and said first anisotropic etch comprises a plasma etching processing utilizing HBr/CO₂/O₂.

15. A method of forming a nonplanar transistor having a multi-cornered body comprising:

forming a photoresist mask on a hard mask film formed on a semiconductor film;

patterning said hard mask film in alignment with said photoresist mask to produce a hard mask;

reducing the width of said photoresist mask to form a reduced width photoresist mask;

etching a first portion of said semiconductor film in alignment with said hard mask;

etching said hard mask in alignment with said reduced width photoresist mask to form a reduced width hard mask;

etching a second portion said semiconductor film in alignment with said reduced width hard mask;

wherein said etching of said first portion and said etching of said second portion to produce a semiconductor body having a top portion and a bottom portion;

removing said hard mask;

forming a gate dielectric layer over said top portion and said bottom portion;

forming a gate electrode on said gate dielectric layer formed on said top portion and said bottom portion of said semiconductor body; and

forming a pair of source/drain regions in said semiconductor body on opposite sides of said gate electrode.

16. The method of claim 15 wherein said gate dielectric layer comprises a high-K gate dielectric.

17. The method of claim 15 wherein said semiconductor film is a silicon film.

18. A method of forming a multi-cornered semiconductor body comprising:

etching a semiconductor film a first time to a first depth in alignment with a hard mask having a first width so as to define a lower body portion having said first width and a first height;

reducing the width of said hard mask to form a reduced width hard mask having a semiconductor;

etching said semiconductor film a second time in alignment with said reduced width hard mask so as to define an upper body portion having said second width and a second height.

19. The method of claim 18 further comprising forming a gate dielectric layer over said lower body portion and said upper body portion of said semiconductor body.

20. The method of claim 18 further comprising forming a gate electrode on said gate dielectric layer on said semiconductor body.