METHOD FOR FORMING TRANSISTOR IN SEMICONDUCTOR DEVICE

• US 20070148841A1
• Filed: 12/27/2006
• Published: 06/28/2007
• Est. Priority Date: 12/28/2005
• Status: Abandoned Application

• Current Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Cho, Pyoung On
• Application Number:
  US11/616,806
• Publication Number:
  US 20070148841A1
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation

Abstract

A method for forming a transistor in a semiconductor device with an elongated channel region. The method includes the steps of forming a polysilicon layer on a semiconductor substrate and patterning the polysilicon layer to form a dummy substrate, and forming a gate oxidation layer and a gate electrode on the semiconductor substrate having the dummy substrate.

Claims

1. A method of forming a transistor in a semiconductor device, the method comprising:

forming a conductive layer on a semiconductor substrate, and patterning the conductive layer to form a dummy substrate; and

forming a gate oxidation layer and a gate electrode on the semiconductor substrate having the dummy substrate.

2. The method of claim 1, wherein the dummy substrate is formed of a polysilicon layer that is the same material as the semiconductor substrate.

3. The method of claim 1, further comprising:

implanting ions on a top surface of the semiconductor substrate having the gate electrode after the gate electrode is formed, and thereby forming source and drain regions.

4. A method of forming a transistor in a semiconductor device, the method comprising:

forming a polysilicon layer on a semiconductor substrate, and patterning the polysilicon layer to form a dummy substrate; and

forming a gate oxidation layer and a gate electrode over the semiconductor substrate having the dummy substrate.

5. The method of claim 4, further comprising:

implanting ions over the top surface of the semiconductor substrate to form lightly doped regions adjacent the gate;

forming spacers along the sidewalls of the gate and oxide regions;

implanting ions on a top surface of the semiconductor substrate, using the gate and spacers as a mask, thereby forming source and drain regions.