NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20070148923A1
• Filed: 03/05/2007
• Published: 06/28/2007
• Est. Priority Date: 07/09/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Kim, Dong Joon, Kim, Sun Woon, Kim, Je Won
• Granted Patent: US 7,687,294 B2
• Time in Patent Office: Days
• US Class Current: 438/483
• CPC Class Codes: H01L 33/14 with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: Y10S 438/962 Quantum dots and lines
• CPC Class Codes: Y10S 438/964 Roughened surface

Abstract

The present invention provides a nitride semiconductor device. The nitride semiconductor device comprises an n-type nitride semiconductor layer formed on a nitride crystal growth substrate. An active layer is formed on the n-type nitride semiconductor layer. A first p-type nitride semiconductor layer is formed on the active layer. A micro-structured current diffusion pattern is formed on the first p-type nitride semiconductor layer. The current diffusion pattern is made of an insulation material. A second p-type nitride semiconductor layer is formed on the first p-type nitride semiconductor layer having the current diffusion pattern formed thereon.

Claims

1. A method of manufacturing a nitride semiconductor device by means of vapor deposition, the method comprising the steps of:

forming an n-type nitride semiconductor layer on a nitride crystal growth substrate;

forming an active layer on the n-type nitride semiconductor layer;

forming a first p-type nitride semiconductor layer on the active layer;

forming a micro-structured current diffusion pattern on the first p-type nitride semiconductor layer, the current diffusion pattern being made of an insulation material; and

forming a second p-type nitride semiconductor layer on the first p-type nitride semiconductor layer having the current diffusion pattern formed thereon.

2. The method as set forth in claim 1, wherein the current diffusion pattern forming step comprises the sub-step of:

forming a silicon nitride (SiN_x) arranged in a nano-sized dot structure.

3. The method as set forth in claim 2, wherein the current diffusion pattern forming step comprises the sub-step of:

supplying silane or tetraethylsilane and ammonia gas to form a silicon nitride pattern having a nano-sized dot structure.

4. The method as set forth in claim 1, further comprising the steps of:

forming a mask pattern on the upper surface of the second p-type nitride semiconductor layer in the same manner as the current diffusion pattern; and

etching the upper surface of the second p-type nitride semiconductor layer through the use of the mask pattern.

5. The method as set forth in claim 1, wherein the thickness of each of the first and second p-type nitride semiconductor layers is approximately 50 Å

to 2000 Å

.

6. The method as set forth in claim 1, wherein the thickness of the current diffusion pattern is not more than approximately 10 Å

.

7. The method as set forth in claim 1, wherein the n-type nitride semiconductor layer forming step comprises the sub-steps of:

forming a first n-type nitride semiconductor layer on the upper surface of the substrate;

forming a silicon nitride pattern on the first n-type nitride semiconductor layer, the silicon nitride pattern being arranged in a nano-sized dot structure; and

forming a second n-type nitride semiconductor layer on the first n-type nitride semiconductor layer having the silicon nitride pattern formed thereon.