Semiconductor devices incorporating carbon nanotubes and composites thereof

• US 20070148963A1
• Filed: 12/27/2005
• Published: 06/28/2007
• Est. Priority Date: 12/27/2005
• Status: Abandoned Application

• Current Assignee: Hong Kong University of Science and Technology
• Original Assignee: Hong Kong University of Science and Technology
• Inventors: Chan, Philip, Zhang, Min, Huo, Xiao
• Application Number:
  US11/318,974
• Publication Number:
  US 20070148963A1
• Time in Patent Office: Days
• US Class Current: 438/637
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 2221/1094 Conducting structures comprising nanotubes or nanowires
• CPC Class Codes: H01L 23/53276 containing carbon, e.g. fullerenes superconducting fullerenes H10N60/853
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods of utilizing carbon nanotubes or composites thereof as hole plugs in vias or in contact holes for connecting conductive layers in integrated circuits are disclosed. Integrated circuits and integrated circuit layers formed by the methods are also disclosed.

Claims

1-39. -39. (canceled)

40. A method of forming an integrated circuit layer comprising the following steps:

depositing an insulating layer on a first conductive layer of an integrated circuit;

patterning the insulating layer to form contact and/or via holes;

forming carbon nanotubes in the contact and/or via holes;

depositing a second conductive layer over the insulating layer;

wherein a catalyst for the formation of carbon nanotubes is present on at least a portion of the first conductive layer before the insulating layer has been deposited on the first conductive layer.

42. A method according to claim 40 wherein the carbon nanotubes are formed by chemical vapor deposition.

43. A method according to claim 40 wherein the insulating layer is planarized prior to the deposition of the second conductive layer.

44. A method according to claim 43 wherein the insulating layer is subjected to a chemical mechanical polish prior to the deposition of the second conductive layer.

45. A method according to claim 40 wherein the catalyst is deposited on the first conductive layer prior to the deposition of the insulating layer on the first conductive layer.

47. A method according to claim 40 wherein the catalyst is a metal catalyst.

48. A method according to claim 47 wherein the catalyst is iron, cobalt, nickel, ruthenium, gold, platinum, or compounds thereof.

49. A method according to claim 40 wherein the carbon nanotubes are formed by chemical vapor deposition (including plasma-enhanced CVD (PECVD), microwave CVD (MWCVD), hot-filament CVD (HFCVD), bias-enhanced CVD, thermal CVD etc.), laser ablation, or arc discharge.

50. A method according to claim 49 wherein the carbon nanotubes are formed by plasma enhanced chemical vapor deposition.

51. A method according to claim 49 wherein the chemical vapor deposition uses a gas selected from methane, ethane, ethylene, acetylene, xylene, and benzene.

52. A method according to claim 51 wherein the gas is mixed with hydrogen or argon.

53. A method according to claim 40 wherein the insulating layer is planarized after the formation of the carbon nanotubes.

54. A method according to claim 40 wherein the carbon nanotubes are treated with a plasma process after the formation of the carbon nanotubes.

55. A method according to claim 53 wherein the insulating layer is subjected to a chemical mechanical polishing process.

56. A method according to claim 40 wherein the first conductive layer and second conductive layer are independently selected from aluminum, copper, and polysilicon.

57. A method according to claim 40 wherein the catalyst layer and the metal layer underneath are patterned at the same lithography step before depositing and pattering the upper insulation layer.

58. An integrated circuit layer made by a method according to claim 40.

59. An integrated circuit comprising an integrated circuit layer made by a method according to claim 40.

41. A method of forming an integrated circuit layer comprising the following steps:

depositing a catalyst layer on a first conductive layer;

depositing an insulating layer on the catalyst layer;

patterning the insulating layer with holes thereby exposing the catalyst layer in the holes;

forming carbon nanotubes in the holes;

depositing a second conductive layer over the insulating layer.

46. A method according to claim 41 wherein the catalyst is deposited on the first conductive layer using a technique selected from physical vapor deposition and solution coating.

60. A method of forming an integrated circuit layer comprising the following steps:

depositing an insulating layer on a first conductive layer of an integrated circuit;

patterning the insulating layer to form contact and/or via holes;

forming carbon nanotube/metal composites in the contact and/or via holes;

depositing a second conductive layer over the insulating layer;

wherein a catalyst for the formation of carbon nanotube/metal catalyst composites is present on at least a portion of the first conductive layer before the insulating layer has been deposited on the first conductive layer.

61. A method according to claim 60 wherein the carbon nanotube/metal composites are formed by chemical vapor deposition.

62. A method according to claim 60 wherein the insulating layer is planarized prior to the deposition of the second conductive layer.

63. A method according to claim 62 wherein the insulating layer is subjected to a chemical mechanical polish prior to the deposition of the second conductive layer.

64. A method according to claim 60 wherein the catalyst is deposited on the first conductive layer prior to the deposition of the insulating layer on the first conductive layer.

65. A method according to claim 64 wherein the catalyst is deposited on the first conductive layer using a technique selected from physical vapor deposition and solution coating.

66. A method according to claim 60 wherein the catalyst is a metal catalyst.

67. A method according to claim 66 wherein the catalyst is iron, cobalt, nickel, ruthenium, gold, platinum, or compounds thereof.

68. A method according to claim 60 wherein the carbon nanotube/metal composites are formed by chemical vapor deposition (including plasma-enhanced CVD (PECVD), microwave CVD (MWCVD), hot-filament CVD (HFCVD), bias-enhanced CVD, thermal CVD etc.), laser ablation, or arc discharge.

69. A method according to claim 68 wherein the carbon nanotube/metal composites are formed by plasma enhanced chemical vapor deposition.

70. A method according to claim 68 wherein the chemical vapor deposition uses a gas selected from methane, ethane, ethylene, acetylene, xylene, and benzene.

71. A method according to claim 70 wherein the gas is mixed with hydrogen or argon.

72. A method according to claim 60 wherein the insulating layer is planarized after the formation of the carbon nanotube/metal composites.

73. A method according to claim 60 wherein the carbon nanotube/metal composites are treated with a plasma process after their formation.

74. A method according to claim 72 wherein the insulating layer is subjected to a chemical mechanical polishing process.

75. A method according to claim 60 wherein the first conductive layer and second conductive layer are independently selected from aluminum, copper, and polysilicon.

76. A method according to claim 60 wherein the catalyst layer and the metal layer underneath are patterned at the same lithography step before depositing and pattering the upper insulation layer.

77. An integrated circuit layer made by a method according to claim 60.

78. An integrated circuit comprising an integrated circuit layer made by a method according to claim 60.