Conditional and vectored system management interrupts
First Claim
Patent Images
1. A method comprising:
- receiving a system management interrupt (SMI), the SMI being associated with a system management mode (SMM);
broadcasting a conditional SMI inter-processor interrupt (IPI) message to at least a processor;
processing the SMI without waiting for the at least processor to check into the SMM; and
broadcasting a clear pending SMI IPI message to the at least processor at end of SMI processing to clear a pending SMI condition.
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Abstract
An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode (SMM). A conditional SMI inter-processor interrupt (IPI) message is broadcast to at least a processor. The SMI is processed without waiting for the at least processor to check into the SMM. A clear pending SMI is broadcast to the processors at end of SMI processing to clear a pending SMI condition.
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Citations
30 Claims
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1. A method comprising:
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receiving a system management interrupt (SMI), the SMI being associated with a system management mode (SMM);
broadcasting a conditional SMI inter-processor interrupt (IPI) message to at least a processor;
processing the SMI without waiting for the at least processor to check into the SMM; and
broadcasting a clear pending SMI IPI message to the at least processor at end of SMI processing to clear a pending SMI condition. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising:
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receiving a conditional system management interrupt (SMI) inter-processor interrupt (IPI) message from a first processor, the SMI being associated with a system management mode (SMM); and
responding to the conditional SMI IPI message according to a current privilege level. - View Dependent Claims (9, 10, 11, 12, 13, 20)
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14. An article of manufacture comprising:
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a machine-accessible medium including data that, when accessed by a machine, cause the machine to perform operations comprising;
receiving a system management interrupt (SMI), the SMI being associated with a system management mode (SMM);
broadcasting a conditional SMI inter-processor interrupt (IPI) message to at least a processor;
processing the SMI without waiting for the at least processor to check into the SMM; and
broadcasting a clear pending SMI IPI message to the at least processor at end of SMI processing to clear a pending SMI condition. - View Dependent Claims (15, 16)
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17. An article of manufacture comprising:
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a machine-accessible medium including data that, when accessed by a machine, cause the machine to perform operations comprising;
receiving a conditional system management interrupt (SMI) inter-processor interrupt (IPI) message from a first processor, the SMI being associated with a system management mode (SMM); and
responding to the conditional SMI IPI message according to a current privilege level. - View Dependent Claims (18, 19)
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21. A method comprising:
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receiving a system management interrupt (SMI) inter-processor interrupt (IPI) message for an SMI event;
obtaining a vector identifier associated with the SMI IPI message;
indexing a vector table using the vector identifier to obtain a pointer to a handler corresponding to the SMI event; and
processing the handler to service the SMI event. - View Dependent Claims (22, 23)
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24. An article of manufacture comprising:
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a machine-accessible medium including data that, when accessed by a machine, cause the machine to perform operations comprising;
receiving a system management interrupt (SMI) inter-processor interrupt (IPI) message for an SMI event;
obtaining a vector identifier associated with the SMI IPI message;
indexing a vector table using the vector identifier to obtain a pointer to a handler corresponding to the SMI event; and
processing the handler to service the SMI event. - View Dependent Claims (25, 26)
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27. A system comprising:
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a chipset generating a system management interrupt (SMI), the SMI being associated with a system management mode (SMM);
a first processor coupled to the chipset and a second processor, the first processor operating at a first privilege level having a first memory containing a first system management interrupt (SMI) handler, the first SMI handler comprising;
a first broadcaster to broadcast a conditional SMI inter-processor interrupt (IPI) message upon receipt of a directed SMI, an SMI processing module to process the SMI, and a second broadcaster to broadcast a clear pending SMI IPI message to the second processor at end of SMI processing to clear a pending SMI condition;
a second processor coupled to the first processor, the second processor operating at a second privilege level and having a second memory containing a second SMI handler, the second SMI handler comprising;
a receiver to receive the SMI IPI message from the first processor, and a responder to respond to the conditional SMI IPI message according to the second privilege level. - View Dependent Claims (28, 29, 30)
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Specification