Fully buffered DIMM read data substitution for write acknowledgement

• US 20070150672A1
• Filed: 12/28/2005
• Published: 06/28/2007
• Est. Priority Date: 12/28/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cheng, Kai, Agarwal, Rajat, Alexander, James, Christenson, Bruce
• Granted Patent: US 7,444,479 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/4234 being a memory bus

Abstract

A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.

Claims

1. A memory controller comprising:

control logic to retire at least two entries in a retirement queue in response to a single response sent from a memory module over a point-to-point memory bus.

2. The memory controller of claim 1 wherein:

a first entry of the at least two entries corresponds to a first memory command to cause a first memory module to read; and

a second entry of the at least two entries corresponds to a second memory command to cause a second memory module to write.

3. The memory controller of claim 2 wherein the first memory module is the memory module and is south of the second memory module.

4. The memory controller of claim 3 wherein the single response corresponds to the first entry and the first memory command.

5. The memory controller of claim 4 wherein the single response includes data read from the first memory module.

6. The memory controller of claim 5 wherein the first memory command directs the second memory module to write concurrently with the first memory module reading.

7. A method comprising:

sending a first memory command causing a first memory module to read;

sending a second memory command causing a second memory module to write, the second memory module being farther north than the first memory module;

designating a first queue entry corresponding to the first memory command and a second queue entry corresponding to the second memory command; and

retiring both queue entries in response to a response originating from the first memory module.

8. The method of claim 7 wherein the response includes data read from the first memory module.

9. The method of claim 7 wherein the response does not correspond to the second memory command.

10. The method of claim 7 wherein a write acknowledgement in response to the second memory command is not received.

11. The method of claim 7 further comprising writing data to the second memory module concurrently with the first memory module reading.

12. The method of claim 7 wherein the first memory command includes a burst length eight read or a back-to-back pair of open-page burst length four reads.

13. A memory apparatus comprising:

control logic to receive a southbound memory read command, the control logic to forward the southbound memory read command to a memory module buffer for a memory module, to receive a memory write command, to forward to a memory controller a northbound response corresponding to the memory read command; and

to determine whether to send a non-error response corresponding to the memory write command.

14. The memory apparatus of claim 13 wherein the memory controller determines that a write occurred based on the northbound response.

15. The memory apparatus of claim 13 wherein the response includes data read from the memory module.

16. The memory apparatus of claim 13 wherein the memory controller retires two entries in a replay queue in response to the northbound response, the northbound response including data read from the memory module.

17. A system comprising:

control logic to send a first memory command to a first memory module;

the first memory module to read in response to the first memory command;

the control logic to send a second memory command to a second memory module, the second memory module being farther south than the first memory module;

the second memory module to write in response to the second memory command;

the control logic to designate a first queue entry corresponding to the first memory command and a second queue entry corresponding to the second memory command; and

the control logic to retire both queue entries in response to a response originating from the first memory module.

18. The system of claim 17 wherein the response includes data read from the first memory module.

19. The system of claim 17 wherein the response does not correspond to the second memory command.

20. The system of claim 17 wherein a write acknowledgement in response to the second memory command is not received.

21. The system of claim 17 further comprising the control logic to write data to the second memory module concurrently with the first memory module reading.

22. The system of claim 18 wherein the first memory command includes a burst length eight read or a back-to-back pair of burst length four reads.