Thin film transistor array substrate and manufacturing method thereof

• US 20070152219A1
• Filed: 12/14/2006
• Published: 07/05/2007
• Est. Priority Date: 12/30/2005
• Status: Abandoned Application

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Lim, Byoung Ho
• Application Number:
  US11/638,513
• Publication Number:
  US 20070152219A1
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/78633 with a light shield

Abstract

A thin film transistor array substrate includes a gate line and a data line intersecting each other on a substrate with a gate insulating film therebetween, a thin film transistor at an intersection of the gate line and the data line, the thin film transistor including a gate electrode electrically connected to the gate line, a semiconductor pattern overlapping the gate electrode with the gate insulating film therebetween, and a source electrode and a drain electrode above the semiconductor pattern, and a pixel electrode contacting the drain electrode of the thin film transistor, the drain electrode substantially completely overlapping at least one of the gate electrode and the gate line.

Claims

1. A thin film transistor array substrate, comprising:

a gate line and a data line intersecting each other on a substrate with a gate insulating film therebetween;

a thin film transistor at an intersection of the gate line and the data line, the thin film transistor including a gate electrode electrically connected to the gate line, a semiconductor pattern overlapping the gate electrode with the gate insulating film therebetween, and a source electrode and a drain electrode above the semiconductor pattern; and

a pixel electrode contacting the drain electrode of the thin film transistor, the semiconductor pattern positioned at a lower portion of the drain electrode substantially completely overlapping at least one of the gate electrode and the gate line.

2. The thin film transistor array substrate as claimed in claim 1, wherein the drain electrode completely overlaps at least one of the gate electrode and the gate line.

3. The thin film transistor array substrate as claimed in claim 1, wherein the gate electrode is a non-protruding portion of the gate line.

4. The thin film transistor array substrate as claimed in claim 1, wherein the pixel electrode includes a protruding portion extending above the drain electrode and the gate line.

5. The thin film transistor array substrate as claimed in claim 1, wherein the source electrode is a protruding portion from the data line and entirely overlaps the gate line.

6. The thin film transistor array substrate as claimed in claim 1, further comprises:

a protective film on the pixel electrode and the thin film transistor, the protective film having a contact hole exposing a region of the drain electrode of the thin film transistor and the pixel electrode electrically contacting the drain electrode via the contact hole.

7. The thin film transistor array substrate as claimed in claim 6, wherein the protective film covers a channel region of the thin film transistor.

8. The thin film transistor array substrate as claimed in claim 1, wherein the thin film transistor includes:

a channel region between the source electrode and the drain electrode, and

an oxide film on an upper surface of the channel region.

9. The thin film transistor array substrate as claimed in claim 1, wherein a portion of the pixel electrode overlaps the gate line to form a storage capacitor with the gate insulating film and a protective film therebetween.

10. The thin film transistor array substrate as claimed in claim 1, wherein a portion of the pixel electrode overlaps the gate line to form a storage capacitor with only the gate insulating film therebetween.

11. A method of fabricating a thin film transistor array substrate, comprising:

forming a gate pattern on a substrate, the gate pattern including a gate line and a gate electrode electrically connected to the gate line;

forming a gate insulating film covering the gate pattern;

forming a semiconductor pattern and a source/drain pattern on the gate insulating film, the source/drain pattern including a data line intersecting the gate line, a source electrode electrically connected to the data line, and a drain electrode opposed to the source electrode; and

forming a pixel electrode contacted the drain electrode, the semiconductor pattern positioned at a lower portion of the drain electrode substantially completely overlapping at least one of the gate electrode and the gate line.

12. The method as claimed in claim 11, wherein the forming the gate pattern includes forming the gate electrode as a non-protruding portion of the gate line.

13. The method as claimed in claim 11, wherein the forming the pixel electrode includes forming a protruding portion extending above the drain electrode and the gate line.

14. The method as claimed in claim 11, wherein the forming the source/drain pattern includes forming the source electrode as a protruding portion from the data line, wherein the source electrode and the drain electrode are formed to entirely overlap the gate line.

15. The method as claimed in claim 11, further comprises:

forming a protective film on the gate insulating film, the semiconductor pattern and the source/drain pattern prior to forming the pixel electrode; and

forming a contact hole in the protective film, the contact hole exposing a region of the drain electrode, the pixel electrode electrically contacting the drain electrode via the contact hole.

16. The method as claimed in claim 11, further comprising:

forming an oxide film on an upper surface of a channel between the source electrode and the drain electrode.

17. The method as claimed in claim 16, wherein the forming the oxide film includes introducing O₂ plasma onto the substrate.

18. The method as claimed in claim 11, wherein the forming the pixel electrode includes forming a portion of the pixel electrode to overlap the gate line to form a storage capacitor with only the gate insulating film therebetween.

19. The method as claimed in claim 11, wherein the forming the pixel electrode includes forming a portion overlapping the gate line to form a storage capacitor with the gate insulating film and a protective film therebetween.

20. The method as claimed in claim 11, wherein the forming the source/drain pattern and the semiconductor pattern including a photolithography and etching process using a diffractive exposure mask.

21. A thin film transistor array substrate, comprising:

a gate line and a data line intersecting each other on a substrate;

a thin film transistor provided at each intersection between the data line and the gate line; and

a pixel electrode electrically connected to the thin film transistor, the thin film transistor being composed of the gate line, a source electrode electrically connected to the data line, a drain electrode opposed to the source electrode, and a semiconductor pattern, wherein the gate line shields light from being incident onto the semiconductor pattern.