Semiconductor device and method for manufacturing the same

• US 20070152245A1
• Filed: 12/27/2006
• Published: 07/05/2007
• Est. Priority Date: 12/29/2005
• Status: Active Grant

• Current Assignee: Columba Technologies, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Ko, Kwang
• Granted Patent: US 7,541,641 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

Disclosed is a semiconductor device. The semiconductor device includes; a pair of drift regions formed in a semiconductor substrate; a trench region formed between the pair of drift regions; an oxide layer spacer on both sidewalls of the trench region; a gate formed in the trench region; and a source and a drain formed in the pair of the drift regions, respectively.

Claims

1. A semiconductor device comprising:

first and second drift regions in a semiconductor substrate;

a trench region between the first and second drift regions;

an oxide layer spacer on sidewalls of the trench region;

an insulating layer below the trench region;

a gate in the trench region; and

a source in one of the first and second drift regions and a drain in the other of the first and second drift regions.

2. The semiconductor device according to claim 1, wherein the trench region has a depth that is equal to or less than that of the first and second drift regions.

3. The semiconductor device according to claim 1, wherein the gate includes a spacer on sidewalls thereof.

4. The semiconductor device according to claim 3, wherein the spacer comprises silicon nitride.

5. The semiconductor device according to claim 1, wherein the first and second drift regions are spaced apart from each other in a horizontal direction.

6. The semiconductor device according to claim 1, wherein the first and second drift regions each have a depth that is greater than a width thereof.

7. The semiconductor device according to claim 1, further comprising an oxide layer adjacent to the trench region.

8. The semiconductor device according to claim 8, wherein a part of the gate is on the upper surface of the oxide layer.

9. A method for manufacturing a semiconductor device, the method comprising the steps of:

forming first and second drift regions in a semiconductor substrate;

forming an oxide layer on the substrate such that the oxide layer partially overlaps the first and second drift regions;

forming a trench between the first and second drift regions;

forming an oxide spacer on sidewalls of the trench;

forming an insulating layer at a bottom of the trench;

forming a gate in the trench and on the oxide layer; and

forming a source in one of the first and second drift regions and a drain in the other of the first and second drift regions.

10. The method according to claim 9, wherein the step of forming the oxide layer includes:

forming a mask pattern on the substrate;

etching the substrate to a predetermined depth;

depositing the oxide layer over an entire surface of the semiconductor substrate; and

planarizing the oxide layer.

11. The method according to claim 9, wherein the trench has a depth equal to or less than that of the first and second drift regions and a width equal to or less than a length of the oxide layer.

12. The method according to claim 11, wherein the width of the trench is less than the length of the oxide layer.

13. The method according to claim 9, further comprising forming a spacer on sidewalls of the gate.

14. The method according to claim 13, wherein the spacer comprises silicon nitride.

15. The method according to claim 9, wherein the first and second drift regions are symmetrical to and spaced apart from each other in a horizontal direction.

16. A method for manufacturing a semiconductor device, the method comprising the steps of:

forming first and second drift regions in a semiconductor substrate;

forming an oxide layer on the substrate such that the oxide layer overlaps with each of the first and second drift regions;

forming a nitride layer on the substrate;

forming a trench between the first and second drift regions;

forming an oxide spacer on sidewalls of the trench;

forming an insulating layer at a bottom of the trench;

removing the nitride layer;

forming a gate in the trench region and at least partially on the oxide layer; and

forming a source in one of the first and second drift regions and a drain in the other of the first and second drift regions.

17. The method according to claim 16, wherein the trench has a depth less than that of the first and second drift regions and a width less than a length of the oxide layer.

18. The method according to claim 16, further comprising forming a nitride spacer on sidewalls of the gate.