DEVICE AND METHOD FOR READING A CAPACITIVE SENSOR, IN PARTICULAR OF A MICRO-ELECTROMECHANICAL TYPE

• US 20070152682A1
• Filed: 11/30/2006
• Published: 07/05/2007
• Est. Priority Date: 12/02/2005
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Lasalandra, Ernesto, Ungaretti, Tommaso
• Granted Patent: US 7,595,648 B2
• Time in Patent Office: Days
• US Class Current: 324/678
• CPC Class Codes: G01P 15/125 by capacitive pick-up

Abstract

A read device of a capacitive sensor includes: a signal source supplying an electrical read signal for driving the capacitive sensor; and a discrete-time sense circuit for generating an electrical output signal, correlated to variations of capacitance of the capacitive sensor, in response to variations of the electrical read signal. The device moreover includes: a modulator stage for generating a modulated electrical read signal on the basis of the electrical read signal and supplying the modulated electrical read signal to the capacitive sensor; a demodulator stage, connected to the sense circuit, for demodulating the electrical output signal and generating a demodulated electrical output signal; and a low-pass filtering stage for generating a filtered electrical output signal, on the basis of the modulated electrical output signal.

Claims

1. A read device of a capacitive sensor, comprising:

a signal source supplying a first electrical read signal for driving said capacitive sensor;

a modulator stage associated with said signal source and structured to generate a modulated second electrical read signal based on said first electrical read signal and supplying said second electrical read signal to said capacitive sensor;

a discrete-time sense circuit, connectable to said capacitive sensor, for generating a first electrical output signal, correlated to capacitance variations of said capacitive sensor, in response to variations of said first electrical read signal;

a demodulator stage , connected to said sense circuit, for demodulating said first electrical output signal and generating a demodulated second electrical output signal; and

a low-pass filtering stage, connected to said demodulator stage, for generating a filtered third electrical output signal, on the basis of said second electrical output signal.

2. The device according to claim 1, wherein said modulator stage is controlled so that said second electrical read signal presents a positive step variation in a first read cycle and a negative step variation in a second read cycle consecutive to said first read cycle.

3. The device according to claim 2, wherein said signal source and said modulator stage are formed by a single circuit forming a modulated signal source.

4. The device according to claim 3, wherein said modulated signal source comprises:

a first line, set at a first voltage;

a second line, supplying a second voltage;

an output terminal for connection to the capacitive sensor;

read connection means for selectively connecting said terminal to said first line and to said second line; and

sense timing means for controlling said read connection means.

5. The device according to claim 4, wherein said read connection means are controlled by said first timing means so as to connect said terminal in sequence to said first line and to said second line during said first read cycle and so as to connect said terminal in sequence to said second line and to said first line during said second read cycle.

6. The device according to claim 2, comprising reset connection means and reset timing means for selectively bringing said sense circuit into a reset configuration both during said first read cycle and during said second read cycle.

7. The device according to claim 1, wherein said demodulator stage comprises:

a first input and a second input;

a first output and a second output;

direct-connection means for selectively connecting said first input to said first output and said second input to said second output; and

crossed-connection means for selectively connecting said first input to said second output and said second input to said first output.

8. The device according to claim 7, wherein said demodulator stage comprises demodulation timing means for controlling said direct connection means and said crossed-connection means for connecting said first input to said first output and said second input to said second output during said first read cycle and for connecting said first input to said second output and said second input to said first output during said second read cycle.

9. The device according to claim 1, wherein said filtering stage is configured so as to calculate a mean value of said second electrical output signal on a even number of samples.

10. The device according to claim 1, wherein said filtering stage includes a discrete-time analog filter.

11. The device according to claim 1, wherein said filtering stage includes a low-pass sigma-delta analog-to-digital converter.

12. The device according to claim 1, wherein said filtering stage includes a numeric filter.

13. The device according to claim 1, wherein said sense circuit comprises a charge-voltage converter.

14. The device according to claim 13, wherein said charge-voltage converter comprises a fully differential switched-capacitor charge amplifier.

15. The device according to claim 13, wherein said sense circuit comprises an offset canceling stage associated to said charge-voltage converter.

16. A detecting apparatus comprising:

a capacitive sensor; and

a read device that includes;

a signal source supplying a first electrical read signal for driving said capacitive sensor;

a modulator stage associated with said signal source and structured to generate a modulated second electrical read signal based on said first electrical read signal and supplying said second electrical read signal to said capacitive sensor;

a discrete-time sense circuit connectable to said capacitive sensor and structured to generate a first electrical output signal, correlated to capacitance variations of said capacitive sensor, in response to variations of said first electrical read signal;

a demodulator stage connected to said sense circuit and structured to demodulate said first electrical output signal and generate a demodulated second electrical output signal; and

a low-pass filtering stage connected to said demodulator stage and structured to generate a filtered third electrical output signal based on said second electrical output signal.

17. The apparatus according to claim 16, wherein said capacitive sensor is a differential micro-electromechanical sensor.

18. The apparatus according to claim 16, wherein said modulator stage is controlled so that said second electrical read signal presents a positive step variation in a first read cycle and a negative step variation in a second read cycle consecutive to said first read cycle.

19. The apparatus according to claim 16, wherein said signal source and said modulator stage are formed by a single circuit forming a modulated signal source, wherein said modulated signal source comprises:

a first line, set at a first voltage;

a second line, supplying a second voltage;

an output terminal for connection to the capacitive sensor;

first and second switches that selectively connect said terminal to said first line and to said second line; and

a phase generator structured to provide phased first and second control signals to the first and second switches.

20. The apparatus according to claim 16, wherein said demodulator stage comprises:

a first input and a second input;

a first output and a second output;

first and second switches that selectively connect said first input to said first output and said second input to said second output; and

third and fourth switches that selectively connect said first input to said second output and said second input to said first output.

21. The apparatus according to claim 20, wherein said demodulator stage comprises demodulation timing means for controlling said switches in a manner that connects said first input to said first output and said second input to said second output during a first read cycle and connects said first input to said second output and said second input to said first output during a second read cycle that is consecutive to the first read cycle.

22. A detecting apparatus comprising:

a processing unit;

a capacitive sensor; and

a read device coupled to the processing unit and including;

a signal source supplying a first electrical read signal for driving said capacitive sensor;

a modulator stage associated with said signal source and structured to generate a modulated second electrical read signal based on said first electrical read signal and supplying said second electrical read signal to said capacitive sensor;

a discrete-time sense circuit connectable to said capacitive sensor and structured to generate a first electrical output signal, correlated to capacitance variations of said capacitive sensor, in response to variations of said first electrical read signal; and

a demodulator stage connected to said sense circuit and structured to demodulate said first electrical output signal and generate a demodulated second electrical output signal.

23. The apparatus according to claim 22 wherein the processing unit includes a low-pass filtering stage connected to said demodulator stage and structured to generate a filtered third electrical output signal based on said second electrical output signal.

24. The apparatus according to claim 22 wherein the apparatus is a portable phone.

25. The apparatus according to claim 22, wherein said modulator stage is controlled so that said second electrical read signal presents a positive step variation in a first read cycle and a negative step variation in a second read cycle consecutive to said first read cycle.

26. The apparatus according to claim 22, wherein said signal source and said modulator stage are formed by a single circuit forming a modulated signal source, wherein said modulated signal source comprises:

a first line, set at a first voltage;

a second line, supplying a second voltage;

an output terminal for connection to the capacitive sensor;

first and second switches that selectively connect said terminal to said first line and to said second line; and

a phase generator structured to provide phased first and second control signals to the first and second switches.

27. The apparatus according to claim 22, wherein said demodulator stage comprises:

a first input and a second input;

a first output and a second output;

first and second switches that selectively connect said first input to said first output and said second input to said second output; and

third and fourth switches that selectively connect said first input to said second output and said second input to said first output.

28. The apparatus according to claim 27, wherein said demodulator stage comprises demodulation timing means for controlling said switches in a manner that connects said first input to said first output and said second input to said second output during a first read cycle and connects said first input to said second output and said second input to said first output during a second read cycle that is consecutive to the first read cycle.

29. The method for reading a capacitive sensor, comprising the steps of:

generating a first electrical read signal for driving the capacitive sensor; and

modulating said electrical read signal for generating a modulated second electrical read signal;

driving said capacitive sensor by said second electrical read signal;

discrete-time generating a first electrical output signal correlated to variations of capacitance of said capacitive sensor, in response to variations of said first electrical read signal;

demodulating said first electrical output signal for generating a demodulated second electrical output signal; and

low-pass filtering said second electrical output signal for generating a filtered third electrical output signal.

30. The method according to claim 29, wherein said second electrical read signal presents a positive step variation in a first read cycle and a negative step variation in a second read cycle consecutive to said first read cycle.

31. The method according to claim 30, wherein said step of modulating comprises:

connecting, during said first read cycle, a driving terminal of said capacitive sensor in sequence to a first line, set at a first voltage, and to a second line, supplying a second voltage; and

connecting, during said second read cycle, said driving terminal in sequence to said second line and to said first line.

32. The method according to claim 31, wherein said step of connecting during said first read cycle comprises first timing read connection means, set between said driving terminal, said first line, and said second line, and said step of connecting during said second read cycle comprises second timing said read connection means.

33. The method according to claim 30, comprising the steps of:

connecting a sense circuit to said capacitive sensor; and

bringing said sense circuit into a reset configuration both during said first read cycle and during said second read cycle.

34. The method according to claim 30, wherein said demodulating step comprises:

supplying said first electrical output signal between a first terminal and a second terminal;

supplying said second electrical output signal between a third terminal and a fourth terminal;

connecting said first terminal to said third terminal and said second terminal to said fourth terminal during said first read cycle; and

connecting said first terminal to said fourth terminal and said second terminal to said third terminal during said second read cycle.

35. The method according to claim 30, wherein said sense circuit comprises a fully differential switched-capacitor charge amplifier.

36. The method according to claim 29, wherein said step of low-pass filtering comprises calculating a mean value of said second electrical output signal on an even number of samples.

37. The method according to claim 36, wherein said step of low-pass filtering comprises executing an analog-to-digital conversion by a low-pass sigma-delta converter.