MPGA products based on a prototype FPGA

• US 20070152708A1
• Filed: 03/01/2007
• Published: 07/05/2007
• Est. Priority Date: 07/08/2002
• Status: Active Grant

• Current Assignee: Yakimishu Co Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Tier Logic, Inc.
• Inventors: Madurawe, Raminda, White, Thomas, Suaris, Peter
• Granted Patent: US 7,673,273 B2
• Time in Patent Office: Days
• US Class Current: 326/39
• CPC Class Codes: G06F 2115/06 Structured ASICs
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A smaller mask programmable gate array (MPGA) device derived from a larger field programmable gate array (FPGA), comprising: a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the FPGA; and input/output pads matching a subset of the input/output pads of the FPGA; wherein, a design that is mapped to said smaller region of the FPGA device using said subset of input/output pads by a user programmable means can be identically mapped to the MPGA by a hard-wire circuit. Such a gate array further comprises a mask programmable metal-circuit in lieu of a user programmable configuration circuit of the FPGA; and a logic block to input/output pad connection in lieu of a logic block to a register at the boundary of said smaller region to an input/output pad connection of the FPGA.

Claims

1. An integrated circuit design platform, comprising:

a field programmable gate array (FPGA) prototype device comprised of;

a circuits layout comprising a plurality of field programmable logic blocks and a plurality of layers of field programmable interconnects; and

a set of input/output pad structures; and

a first region within the circuits layout, said region having registers at one or more boundaries of the region, a said register capable of coupling to a said input/output pad structure; and

a first metal programmable gate array (first MPGA) production device comprised of;

a substantially identical circuits layout as in the first region of the FPGA; and

a substantially identical layout of one or more layers of programmable interconnects as in the first region of the FPGA;

wherein, a design mapped to the first region of the FPGA is identically mapped to the first MPGA.

2. The design platform of claim 1, wherein the FPGA comprises a configuration circuit to field program the programmable logic blocks and programmable interconnects.

3. The design platform of claim 2, wherein in the FPGA, the transistors for logic circuits are formed on a first module layer and the configuration circuit is formed on a second module layer positioned substantially above the first module layer.

4. The design platform of claim 2, wherein the configuration circuit comprises one or more of:

resistor, capacitor, SRAM cell, DRAM cell, Flash cell, EPROM cell, EEPROM cell, Carbon nano-tube, resistance modulating element, ferro-electric element, electro-chemical cell, electro-mechanical element, optical element and electro-magnetic cell.

5. The design platform of claim 1, wherein the MPGA comprises a customized metal circuit to mask program the programmable logic blocks and programmable interconnects.

6. The platform of claim 5, wherein the customized metal circuit comprises one or more of:

wire connection, wire disconnect, via connection, resistor element, shorted capacitor, capacitor, power bus connection, ground bus connection, transistor short, logic zero output connection, and logic one output connection.

7. The platform of claim 1, wherein said first region of the FPGA and said first MPGA further comprises a substantially identical layout of one or more pass-gate devices to couple a said programmable logic block to a said interconnect wire, wherein:

in the FPGA, the pass-gate device couples the logic block to the interconnect wire, said pass-gate device controlled by an output of a RAM bit, said RAM bit comprising;

a logic one to couple the logic block to the interconnect wire; and

a logic zero to decouple the logic block from the interconnect wire; and

in the MPGA, the pass-gate device couples the logic block to the interconnect wire, said pass-gate device controlled by an output of a ROM bit, said ROM bit comprising;

a metal connection to power bus to couple the logic block to the interconnect wire; and

a metal connection to ground bus to decouple the logic block from the interconnect wire.

8. The platform of claim 1, wherein said first region of the FPGA and said first MPGA further comprises a substantially identical layout of one or more pass-gate devices to couple said one or more logic blocks to a said interconnect wire, wherein:

in the FPGA, a pass-gate device couples a logic block to an interconnect wire, said pass-gate device controlled by an output of a RAM bit, said RAM bit comprising;

a logic one to couple the logic block to the interconnect wire; and

a logic zero to decouple the logic block from the interconnect wire; and

in the MPGA, said pass-gate device is decoupled from said interconnect wire when the RAM bit comprises a logic zero;

wherein an interconnect wire in the FPGA comprises a high capacitance due to the pass-gate device junctions coupled to the interconnect wire, and wherein said interconnect wire in the MPGA comprises less capacitance due to the pass-gate junctions decoupled from the interconnect wire.

9. The platform of claim 1, wherein said first region of the FPGA and said first MPGA further comprises a substantially identical layout of one or more pass-gate devices to couple said one or more logic blocks to a said interconnect wire, wherein:

in the FPGA, a pass-gate device couples a logic block to an interconnect wire, said pass-gate device controlled by an output of a RAM bit, said RAM bit comprising;

a logic one to couple the logic block to the interconnect wire; and

a logic zero to decouple the logic block from the interconnect wire; and

in the MPGA, said pass-gate device is replaced by a metal jumper when the RAM bit comprises a logic one;

wherein an interconnect wire coupled to a logic block encounters a high resistance from the on pass-gate device in the FPGA, and wherein said interconnect wire coupled to the logic block in the MPGA encounters less resistance due to the metal-jumper.

10. The platform of claim 1, further comprising:

said field programmable gate array (FPGA) prototype device comprised of;

a second region within the circuits layout, said second region having registers at one or more boundaries of the region, a said register capable of coupling to a said input/output pad structure; and

a second metal programmable gate array (second MPGA) production device comprised of;

a substantially identical circuits layout as in the second region of the FPGA; and

a substantially identical layout of one or more layers of programmable interconnects as in the second region of the FPGA;

wherein, a design mapped to the second region of the FPGA is identically mapped to the second MPGA.

11. An integrated circuit design platform, comprising:

a prototype field programmable (FPGA) device comprising a layout of electronic circuits and input/output pads; and

a production mask programmable (MPGA) device comprising;

a layout of electronic circuits substantially identical to a region within the prototype FPGA; and

a subset of input/output pads as within the prototype FPGA;

wherein a design placed and routed within the region of the prototype FPGA using the subset of input/output pads as in the production MPGA, is identically placed and routed in the production MPGA.

12. The platform of claim 11, wherein the said region of the FPGA and the MPGA has substantially identical layouts of transistors and substantially identical layouts of one or more layers of interconnects.

13. The platform of claim 11, wherein MPGA has at least one customized interconnect layer to map field programmable data in the prototype FPGA to mask programmable data.

14. The platform of claim 11, wherein the FPGA comprises a configuration circuit further comprising one or more of:

resistor, capacitor, SRAM cell, DRAM cell, Flash cell, EPROM cell, EEPROM cell, Carbon nano-tube, resistance modulating element, ferro-electric element, electro-chemical cell, electro-mechanical element, optical element and electro-magnetic cell.

15. The platform of claim 11, wherein the MPGA comprises a customized metal circuit further comprising one or more of:

wire connection, wire disconnect, via connection, resistor element, shorted capacitor, capacitor, power bus connection, ground bus connection, transistor short, logic zero output connection, and logic one output connection.

16. The platform of claim 11, wherein the FPGA comprises a RAM bit, and wherein the MPGA comprises a hard-wired ROM bit.

17. The platform of claim 11, wherein the MPGA comprises one or more of:

a metal link to couple a node to a power supply voltage; and

a metal link to couple a node to a ground supply voltage; and

a metal jumper to short two nodes; and

a metal disconnect to isolate two nodes.

18. A smaller mask programmable gate array (MPGA) device derived from a larger field programmable gate array (FPGA) device, comprising:

a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the FPGA device; and

input/output pads matching a subset of the input/output pads of the FPGA;

wherein, a design that is mapped to said smaller region of the FPGA device using said subset of input/output pads by a user programmable means is identically mapped to the MPGA by a hard-wire circuit.

19. The device of claim 18, further comprising:

a mask programmable metal-circuit in lieu of a user programmable configuration circuit of the FPGA; and

a logic block to input/output pad connection in lieu of a logic block to a register at the boundary of said smaller region to an input/output pad connection of the FPGA.

20. The device of claim 18, wherein:

a first set of input/output pad to a first set of logic blocks within the MPGA is identically mapped from that of the FPGA; and

a second set of input/output pad to a second set of logic blocks within the MPGA is mapped from the corresponding logic blocks to registers at region boundary to corresponding input/output pads of the FPGA.