SINGLE AND COMPOSITE BINARY AND MULTI-VALUED LOGIC FUNCTIONS FROM GATES AND INVERTERS

• US 20070152710A1
• Filed: 03/15/2007
• Published: 07/05/2007
• Est. Priority Date: 02/25/2004
• Status: Active Grant

• Current Assignee: Ternarylogic LLC
• Original Assignee: Ternarylogic LLC
• Inventors: Lablans, Peter
• Granted Patent: US 7,355,444 B2
• Time in Patent Office: Days
• US Class Current: 326/59
• CPC Class Codes: H03K 19/0002 Multistate logic H03K19/02 takes precedence
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

Gates or switches for use in circuits implementing ternary and multi-value functions are disclosed. The gates can be optical, mechanical or electrical. The gates can conduct or not conduct when a control input assumes one of multiple states, or when a control input assumes two or more of multiple states. Circuits and methods for implementing ternary and multi-value functions are also disclosed. Corrective design techniques that can be used when a logic expression is incorrectly realized are also disclosed. Circuits that use inverters and gates to realize logic expressions are also provided.

Claims

1. A method for implementing an n-valued logic function with n>

2, comprising;

using a n-valued switch having an input and an output and a control input, wherein;

the input is enabled to receive a signal having one of n states;

the input is connected to the output whenever the control input is in a first of n-states; and

the input is isolated from the output whenever the control input is not in a first of n states; and

using an n-valued inverter.

2. The method as claimed in claim 1, wherein the n-valued inverter is reversible.

3. A device implementing an n-valued logic function with n>

2, comprising;

an n-valued switch having an input and an output and a control input, wherein;

the input is enabled to receive a signal having one of n states;

the input is connected to the output whenever the control input is in a first of n-states; and

the input is isolated from the output whenever the control input is not in a first of n-states; and

an n-valued inverter.

4. The device as claimed in claim 3, wherein the n-valued inverter is reversible.

5. A method for implementing an n-valued logic function with n>

2, having an n by n truth table with n rows and n columns comprising;

implementing a row of the n by n truth table by an n-valued inverter; and

enabling the n-valued inverter by an n-valued switch having a control input.

6. The method as claimed in claim 5, wherein:

the n-valued switch further having an input and an output, wherein;

the input is enabled to receive a signal having one of n states;

the input is connected to the output whenever the control input is in a first of n-states; and

the input is isolated from the output whenever the control input is not in a first of n-states.

7. The method as claimed in claim 5, wherein the n-valued inverter implements a column instead of a row of the n by n truth table.