METHOD OF DRIVING A DUAL GATED MOSFET

• US 20070152729A1
• Filed: 03/06/2007
• Published: 07/05/2007
• Est. Priority Date: 08/23/2002
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Elbanhawy, Alan
• Application Number:
  US11/682,613
• Publication Number:
  US 20070152729A1
• Time in Patent Office: Days
• US Class Current: 327/389
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/6877 the control circuit comprising active elements different from those used in the output circuit
• CPC Class Codes: H03K 2017/6878 using multi-gate field-effect transistors
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption

Abstract

A method of driving a dual-gated MOSFET having a Miller capacitance between the MOSFET gate and drain includes preparing the MOSFET to switch from a blocking mode to a conduction mode by applying to the MOSFET shielding gate a first voltage signal having a first voltage level. The first voltage level is selected to charge the Miller capacitance and thereby reduce switching losses. A second voltage signal is applied to the switching gate to switch the MOSFET from the blocking to the conduction mode. The first voltage signal is then changed to a level selected to reduce the conduction mode drain-to-source resistance and thereby reduce conduction losses. The first voltage signal is returned to the first voltage level to prepare the MOSFET for being switched from the conduction mode to the blocking mode.

Claims

1. A method for driving a dual-gated MOSFET, the dual-gated MOSFET being switchable between conduction and blocking modes, the dual-gated MOSFET having a shielding gate, a switching gate, a gate-to-drain overlap regions and a drain-to-source resistance when the MOSFET is in the conduction mode, said method comprising:

applying a first voltage signal to the shielding gate;

maintaining the first voltage signal at a first voltage level prior to switching the MOSFET from the blocking mode to the conduction mode, the first voltage level being selected to substantially completely charge the gate-to-drain overlap region of the MOSFET; and

further applying a second voltage signal to the switching gate, the second voltage signal switching the MOSFET between the blocking and conduction modes.

2. The method of claim 1, wherein said maintaining step comprises one of continuously maintaining the first voltage signal at the first voltage level and maintaining the first voltage signal at the first voltage level for a predetermined amount of time prior to switching the MOSFET from the blocking to the conduction mode.

3. The method of claim 1, wherein said further applying step comprises switching the second voltage signal from a low voltage level to a high voltage level to thereby place the MOSFET in the conduction mode.

4. The method of claim 3, further comprising the steps of:

delaying a first delay time after the further applying step; and

changing the first voltage signal from the first voltage level selected to substantially completely charge the gate-to-drain overlap region of the MOSFET to a fourth voltage level selected to reduce the resistance between the drain and source of the MOSFET while in the conduction mode.

5. The method of claim 4, wherein said first delay time comprises the rise time of the switching gate.

6. The method of claim 4, further comprising the steps of:

returning the first voltage signal from the fourth voltage level selected to reduce the resistance between the drain and source of the MOSFET while in the conduction mode to one of the first voltage level selected to substantially completely charge the gate-to-drain overlap region of the MOSFET or ground potential;

delaying a second delay time; and

further returning the second voltage signal from the high voltage level to the low voltage level to a thereby place the MOSFET in the blocking mode.

7. The method of claim 6, wherein said second delay time comprises the fall time of the shielding gate.

8. A method of driving a dual-gated MOSFET, the dual-gated MOSFET having a shielding gate, a switching gate, a Miller capacitance between the MOSFET gate and drain, and a drain-to-source resistance when the MOSFET is in the conduction mode, said method comprising:

preparing the MOSFET to switch from the blocking mode to the conduction mode by applying a first voltage signal at a first voltage level to the shielding gate, the first voltage level being selected to substantially completely charge the Miller capacitance and thereby reduce switching losses; and

applying a second voltage signal to the switching gate to switch the MOSFET between the blocking and conduction modes.

9. The method of claim 8, further comprising:

delaying a first delay time following said applying step; and

changing the first voltage signal to a fourth voltage level selected to substantially reduce the resistance between the drain and source of the MOSFET to thereby reduce conduction losses.

10. The method of claim 9, wherein said first delay time comprises the rise time of the switching gate.

11. The method of claim 9, further comprising the step of returning the first voltage signal to the first voltage level to thereby substantially completely discharge the Miller capacitance thereby preparing the MOSFET to switch from the conduction mode to the blocking mode.

12. The method of claim 11, further comprising the steps of:

further delaying a second delay time following said returning step; and

switching said second voltage signal to said low voltage level.

13. The method of claim 8, wherein said preparing step comprises one of continuously maintaining the first voltage signal at the first voltage level or maintaining the first voltage signal at the first voltage level for a predetermined amount of time prior to switching the MOSFET from the blocking to the conduction mode.

14. The method of claim 8, wherein said preparing step comprises one of continuously maintaining the first voltage signal at the first voltage level or maintaining the first voltage signal at the first voltage level for a predetermined amount of time prior to switching the MOSFET from the blocking to the conduction mode.