Array substrate for IPS-mode LCD device and method of fabricating the same

• US 20070153198A1
• Filed: 12/15/2006
• Published: 07/05/2007
• Est. Priority Date: 12/29/2005
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Choi, Young-Seok, Ahn, Byung-Yong, Min, Dong-Jun, Jung, Bo-Kyoung, Hwang, Tae-Ung, Cho, Ki-sul
• Granted Patent: US 7,796,225 B2
• Time in Patent Office: Days
• US Class Current: 349/141
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]

Abstract

Provided is an array substrate for an IPS-mode LCD device and method of fabricating the same that prevents a problem referred to as wavy noise. The IPS-mode LCD device and method have a shorter processing time and low error rate without an increase in fabrication and production costs.

Claims

1. An array substrate for an IPS-mode LCD device, comprising:

a substrate having a switching region and a pixel region;

a gate line on the substrate;

a gate electrode formed in the switching region and extending from the gate line;

a common line substantially parallel to the gate line and separated from the gate line;

first and second common electrodes extending from the common line into the pixel region and separated from each other;

a gate insulating layer on the gate line, the common line and the first and second common electrodes, wherein the gate insulating layer has a common line contact hole exposing the common line;

a data line crossing the gate line to define the pixel region on the gate insulating layer;

a semiconductor layer corresponding to the gate electrode on the gate insulating layer;

a source electrode and a drain electrode separated from each other on the semiconductor layer, wherein the source electrode extends from the data line;

a plurality of pixel electrodes between the first and second common electrodes, wherein the plurality of pixel electrodes are separated from each other and substantially parallel to the first and second common electrodes, and each of the plurality of pixel electrodes extends from the drain electrode; and

a plurality of third common electrodes formed on the gate insulating layer, wherein the plurality of third common electrodes are connected to the common line through the common line contact hole and alternately arranged with the plurality of pixel electrodes,

wherein the data line, the plurality of pixel electrodes and the plurality of third common electrodes are formed on a same layer and with a same material as one another.

2. The array substrate according to claim 1, wherein the first and second common electrodes are formed at opposite sides of the pixel region.

3. The array substrate according to claim 1, wherein the common line includes first and second common lines substantially parallel to each other.

4. The array substrate according to claim 3, wherein each of the first and second common electrodes are connected to the first and second common lines and are adjacent to the data line.

5. The array substrate according to claim 3, wherein the common line contact hole exposes the first common line.

6. The array substrate according to claim 3, further comprising a storage capacitor including the second common line, a storage electrode extending from the drain electrode such that the storage electrode overlaps the second common line and the gate insulating layer interposed between the second common line and the storage electrode.

7. The array substrate according to claim 1, wherein the gate line is on a same layer as the first and second common electrodes with a same material as the first and second common electrodes.

8. The array substrate according to claim 1, wherein the gate line, the gate electrode, the first common electrode and the second common electrode have one of a double-layered structure and a triple-layered structure.

9. The array substrate according to claim 8, wherein an uppermost layer of the gate line, the gate electrode, the first common electrode and the second common electrode is a transparent conductive material.

10. The array substrate according to claim 1, further comprising a gate pad electrode and a data pad electrode, wherein the gate pad electrode is connected to the gate line and an external gate driving circuit, and the data pad electrode is connected to the data line and an external data driving circuit.

11. The array substrate according to claim 10, wherein the gate pad electrode and the data pad electrode are on a same layer and a same material as the gate line.

12. The array substrate according to claim 11, wherein the data pad electrode is connected to the data line through a data link line, wherein the data link line is on a same layer as the gate line and a same material as the gate line.

13. The array substrate according to claim 12, wherein the gate insulating layer includes a data link line contact hole exposing an end of the data link line, wherein the data line is connected to the data link line through the data link line contact hole.

14. The array substrate according to claim 11, wherein the gate insulating layer includes a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode.

15. The array substrate according to claim 1, wherein the source electrode and the drain electrode cover ends of the semiconductor layer.

16. The array substrate according to claim 1, further comprising a silicon oxide layer formed on the semiconductor layer between the source and drain electrodes.

17. The array substrate according to claim 1, wherein the semiconductor layer includes an active layer of intrinsic amorphous silicon and an ohmic contact layer of impurity-doped amorphous silicon layer on the active layer.

18. A method of fabricating an array substrate for an IPS-mode LCD device, comprising:

forming a gate line, a gate electrode, a first common line, and first and second common electrodes on a substrate having a switching region and a pixel region using a first mask process, wherein the gate electrode extends from the gate line and is formed in the switching region, the first common line is substantially parallel to the gate line, and the first and second common electrodes extend from the first common line into the pixel region;

sequentially forming a gate insulating layer, an intrinsic amorphous silicon layer and an impurity-doped amorphous silicon layer on the gate line, the gate electrode, and the first and second common electrodes;

forming a common line contact hole in the gate insulating layer, an active layer and an impurity-doped amorphous silicon pattern by patterning the gate insulating layer, the intrinsic amorphous silicon layer and the impurity-doped amorphous silicon layer using a second mask process, wherein the common line contact hole exposes the first common line, the active layer corresponds to the gate electrode on the gate insulating layer and the impurity-doped amorphous silicon pattern has a same shape as the active layer on the active layer; and

forming a data line, a source electrode, a drain electrode, a plurality of pixel electrodes and a plurality of third common electrodes on the gate insulating layer, the active layer and the impurity-doped amorphous silicon pattern using a third mask process, wherein the data line crosses the gate line to define the pixel region, the source electrode extends from the data line and contacts the impurity-doped amorphous silicon pattern, and the drain electrode is separated from the source electrode and contacts the impurity-doped amorphous silicon pattern, wherein the plurality of pixel electrodes are separated each other and substantially parallel to the first and second common electrodes, and each of the plurality of electrodes extends from the drain electrode, and wherein the plurality of third common electrodes contact the first common line through the common line contact hole and are alternately arranged with the plurality of pixel electrodes.

19. The method according to claim 18, further comprising removing the impurity-doped amorphous silicon pattern between the source and drain electrodes to expose the active layer.

20. The method according to the claim 19, further comprising forming a silicon oxide layer on the active layer exposed between the source and drain electrodes.

21. The method according to the claim 18, wherein forming the gate line, the gate electrode, and the first and second electrodes common includes:

forming a first metal layer on the substrate;

forming a transparent conductive layer on the first metal layer; and

sequentially patterning the transparent conductive layer and the first metal layer.

22. The method according to the claim 21, further comprising:

forming a second metal layer between the first metal layer and the transparent conductive layer; and

patterning the second metal layer between the step of patterning the transparent conductive layer and the step of forming the first metal layer.

23. The method according to claim 18, wherein forming the common line contact hole, the active layer and the impurity-doped amorphous silicon pattern includes:

forming a photoresist (PR) layer on the impurity-doped amorphous silicon layer;

providing a mask having a transmissive area, a blocking area and a half-transmissive area over the PR layer;

forming a first PR pattern and second PR patterns by exposing and developing the PR layer using the mask, wherein the first PR pattern corresponds to the gate electrode, and the second PR patterns expose the impurity-doped amorphous silicon layer corresponding to a symmetrical portion of the first common line and have a lower height than the first PR pattern;

forming the common line contact hole by sequentially removing the impurity-doped amorphous layer exposed between the second PR patterns, the intrinsic amorphous silicon layer, and the gate insulating layer;

ashing the first and second PR patterns such that the second PR patterns are removed and the impurity-doped silicon pattern is exposed;

forming the active layer and the impurity-doped silicon pattern by sequentially removing the exposed impurity-doped silicon pattern and the intrinsic amorphous silicon layer; and

removing the first PR pattern.

24. The method according to claim 18, further comprising forming a gate pad electrode, a data link line, a data pad electrode, and a second common line, wherein the gate pad electrode is formed at an end of the gate line, the data link line contacts the data line, the data pad electrode extends from the data link line, and the second common line is substantially parallel to the first common line.

25. The method according to claim 24, wherein each of the first and second common electrodes is connected to the first and second common lines, and wherein the first and second common lines and the first and second common electrodes surround the pixel region.

26. The method according to claim 24, wherein the drain electrode overlaps the second common line such that the second common line, the drain electrode and the gate insulating layer interposed between the second common line and the drain electrode form a storage capacitor.

27. The method according to claim 24, wherein the second mask process includes forming a data link line contact hole exposing an end of the data link line, a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode.

28. The method according to claim 18, wherein the source and drain electrodes cover both ends of the semiconductor layer.