Array substrate for in-plane switching mode liquid crystal display device and method of manufacturing the same

• US 20070153202A1
• Filed: 12/21/2006
• Published: 07/05/2007
• Est. Priority Date: 12/29/2005
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Kang, Byung-Koo
• Granted Patent: US 7,612,854 B2
• Time in Patent Office: Days
• US Class Current: 349/141
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance

Abstract

A substrate for a liquid crystal display device includes a gate line along a first direction on a substrate, a data line along a second direction and crossing the gate line to define a pixel region, a thin film transistor on the substrate and electrically connected to the gate and data lines, a pixel electrode in the pixel region and connected to the thin film transistor, and a common electrode in the pixel region, a first capacitance between the data line and the common and pixel electrodes at a first side of the data line being substantially equal to a second capacitance between the data line and the common and pixel electrodes at a second side of the data line.

Claims

1. A substrate for a liquid crystal display device, comprising:

a substrate;

a gate line along a first direction on the substrate;

a data line along a second direction on the substrate, the data line crossing the gate line to define a pixel region, the pixel region having first and second sides opposing one another and first and second areas along the second direction;

a thin film transistor on the substrate, the thin film transistor electrically connected to the gate and data lines;

a pixel electrode on the substrate and electrically connected to the thin film transistor, the pixel electrode including a first vertical part and a second vertical part, the first vertical part at the first side within the first area and the second vertical part at the second side within the second area; and

a common electrode on the substrate, the common electrode including a first vertical portion and a second vertical portion, the first vertical portion at the first side within the second area and the second vertical portion at the second side within the first area.

2. The substrate according to claim 1, wherein the pixel electrode includes first horizontal parts and second horizontal parts, the first and second horizontal parts respectively extending from the first and second vertical parts along the first direction, and

wherein the common electrode includes first horizontal portions and second horizontal portions, the first and second horizontal portions respectively extending from the first and second vertical portions along the first direction.

3. The substrate according to claim 2, wherein the first horizontal parts alternate with the second horizontal portions within the first area, and the first horizontal portions alternate with the second horizontal parts within the second area.

4. The substrate according to claim 3, wherein the first horizontal parts and second horizontal parts have at least one portion in common.

5. The substrate according to claim 1, wherein the first and second vertical parts are disposed at opposite sides of the pixel region along a first diagonal direction, and the first and second vertical portions are disposed at opposite sides of the pixel region along a second diagonal direction.

6. The substrate according to claim 1, further comprising a common line on the substrate, the common electrode electrically connected to the common line.

7. The substrate according to claim 6, wherein the common line overlaps the first and second vertical parts and the first and second vertical portions.

8. The substrate according to claim 7, wherein the common line includes a loop portion having a shape corresponding to a shape of the pixel region.

9. The substrate according to claim 7, wherein the first and second vertical portions contact the common line through contact holes.

10. The substrate according to claim 1, wherein the thin film transistor includes a gate electrode, an active layer, a source electrode and a drain electrode.

11. The substrate according to claim 1, wherein the common electrode and the pixel electrode include a transparent conductive material.

12. A substrate for a liquid crystal display device, comprising:

a substrate;

gate lines along a first direction on the substrate;

data lines along a second direction on the substrate, the data lines crossing the gate lines to define pixel regions, each of the pixel regions having first and second areas along the second direction;

a thin film transistor on the substrate at each crossing point of the gate and data lines;

a pixel electrode on the substrate in each of the pixel regions, the pixel electrode electrically connected to the thin film transistor and including a first vertical part and a second vertical part; and

a common electrode on the substrate in each of the pixel regions, the common electrode including a first vertical portion and a second vertical portion, the first vertical part and the first vertical portion at a first side of each of the data lines, and the second vertical part and the second vertical portion at a second side of each of the data lines.

13. The substrate according to claim 12, wherein the first vertical part and the second vertical portion are disposed in the first area, and the first vertical portion and the second vertical part are disposed in the second area.

14. A substrate for a liquid crystal display device, comprising:

a substrate;

a gate line along a first direction on the substrate;

a data line along a second direction and crossing the gate line to define a pixel region;

a thin film transistor on the substrate and electrically connected to the gate and data lines;

a pixel electrode in the pixel region and connected to the thin film transistor; and

a common electrode in the pixel region, wherein a first capacitance between the data line and the common and pixel electrodes at a first side of the data line is substantially equal to a second capacitance between the data line and the common and pixel electrodes at a second side of the data line.

15. A method of manufacturing a substrate for a liquid crystal display device, comprising:

forming a gate line along a first direction on a substrate;

forming a data line along a second direction, the data line crossing the gate line to define a pixel region, the pixel region having first and second sides opposing one another and first and second areas along the second direction;

forming a thin film transistor electrically connected to the gate and data lines;

forming a first vertical part of a pixel electrode on the substrate at the first side within the first area;

forming a second vertical part of the pixel electrode on the substrate at the second side within the second area, the pixel electrode electrically connected to the thin film transistor;

forming a first vertical portion of a common electrode on the substrate at the first side within the second area; and

forming a second vertical portion of the common electrode on the substrate at the second side within the first area.

16. The method according to claim 15, further comprising:

forming first horizontal parts of the pixel electrode extending from the first vertical part along the first direction;

forming first horizontal portions of the common electrode extending from the first vertical portion along the first direction;

forming second horizontal parts of the pixel electrode extending from the second vertical part along the first direction; and

forming second horizontal portions of the common electrode extending from the second vertical portion along the first direction.

17. The method according to claim 16, wherein the first horizontal parts are formed alternating with the second horizontal portions in the first area, and the first horizontal portions are formed alternating with the second horizontal parts in the second area.

18. The method according to claim 17, wherein the first horizontal parts and second horizontal parts have at least one portion in common.

19. The method according to claim 15, wherein the first and second vertical parts are disposed at opposite sides of the pixel region along a first diagonal direction, and the first and second vertical portions are disposed at opposite sides of the pixel region along a second diagonal direction.

20. The method according to claim 15, further comprising forming a common line on the substrate, the common line overlapping the first and second vertical parts and the first and second vertical portions.

21. The method according to claim 20, wherein the first and second vertical portions contact the common line through contact holes.

22. The method according to claim 15, wherein the forming the thin film transistor includes forming a gate electrode, forming a gate insulating layer, forming an active layer, forming an ohmic contact layer, and forming a source electrode and a drain electrode.

23. The method according to claim 15, wherein the forming the pixel electrode and forming the common electrode are simultaneously performed.

24. The method according to claim 23, wherein the common electrode and the pixel electrode are formed of a transparent conductive material.

25. A method of manufacturing a substrate for a liquid crystal display device, comprising:

forming a gate line, a gate electrode, and a common line on a substrate, the gate line and the common line extending along a first direction;

forming a gate insulating layer on the gate line, the gate electrode and the common line;

forming an active layer and an ohmic contact layer on the gate insulating layer over the gate electrode;

forming a data line, a source electrode and a drain electrode on the ohmic contact layer, the data line extending along a second direction and crossing the gate line to define a pixel region, the pixel region including first and second areas along the second direction;

forming a passivation layer covering the data line, the source electrode and the drain electrode, the passivation layer including a first contact hole and second contact holes, the first contact hole exposing the drain electrode, the second contact holes exposing the common line; and

forming a pixel electrode and a common electrode in the pixel region on the passivation layer, the pixel electrode including a first vertical part and a second vertical part, the common electrode including a first vertical portion and a second vertical portion,

wherein the first vertical part and the first vertical portion are formed at a first side of the data line, and the second vertical part and the second vertical portion are formed at a second side of the data line.

26. The method according to claim 25, wherein the pixel electrode includes first horizontal parts and second horizontal parts and the common electrode further includes first horizontal portions and second horizontal portions, wherein the first horizontal parts extend from the first vertical part along the first direction, the first horizontal portions extend from the first vertical portion along the first direction, the second horizontal parts extend from the second vertical part along the first direction, and the second horizontal portions extend from the second vertical portion along the first direction.

27. The method according to claim 26, wherein the first horizontal parts and second horizontal parts have at least one portion in common.

28. The method according to claim 25, wherein the pixel electrode is connected to the drain electrode through the first contact hole, and the common electrode is connected to the common line through the second contact holes.

29. The method according to claim 25, wherein the first and second vertical parts are disposed at opposite sides of the pixel region along a first diagonal direction, and the first and second vertical portions are disposed at opposite sides of the pixel region along a second diagonal direction.