Configurable inputs and outputs for memory stacking system and method

• US 20070153588A1
• Filed: 12/30/2005
• Published: 07/05/2007
• Est. Priority Date: 12/30/2005
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Janzen, Jeffery
• Granted Patent: US 7,352,602 B2
• Time in Patent Office: Days
• US Class Current: 365/189.30
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/225 Clock input buffers
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/01055 Cesium [Cs]

Abstract

Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin.

Claims

1. A memory device comprising:

a die having a circuit configured to be enabled by a control signal;

an input pin configured to receive the control signal; and

a path selector arranged between the input pin and the circuit and configured to select a signal path to the circuit from the input pin.

2. The memory device of claim 1, wherein the control signal is a chip select signal.

3. The memory device of claim 1, wherein the path selector comprises a multiplexer.

4. The memory device of claim 1, comprising a path selector control circuit comprising a fuse, wherein the path selector control circuit is configured to control the path selector.

5. The memory device of claim 4, wherein the path selector control circuit is configured to provide a high signal when a fuse is blown.

6. The memory device of claim 4, wherein the path selector control circuit is configured to provide a low signal when an antifuse is blown.

7. The memory device of claim 1, comprising memory comprising a plurality of die.

8. A memory module comprising:

a die stack comprising a plurality of memory devices;

a plurality pins disposed within the plurality of memory devices, wherein each of the plurality of pins is configured to receive at least one of a plurality of signals;

a plurality of circuits disposed within each of the plurality of memory devices, wherein each of the plurality of circuits is configured to be enabled by control signals of the plurality of signals; and

a plurality of path selectors configured to selectively provide communicative coupling between the plurality of pins and the plurality of circuits based on the control signals that enable each of the plurality of circuits.

9. The memory module of claim 8, wherein the memory module comprises a dual inline memory module (DIMM).

10. The memory module of claim 8, wherein each of the plurality of memory devices comprises a dynamic random access memory (DRAM) device.

11. The memory module of claim 8, wherein the plurality of signals include a chip select signal, a clock enable signal, an on-die termination signal, and a calibration signal.

12. The memory module of claim 8, wherein the plurality of path selectors comprises at least one multiplexer.

13. The memory module of claim 8, wherein the plurality of path selectors comprises at least one path selector control circuit comprising a fuse or antifuse, wherein the path selector control circuit is configured to control the path selector.

14. The memory module of claim 13, wherein the path selector control circuit is configured to provide a high signal when the fuse is blown.

15. The memory module of claim 13, wherein the path selector control circuit is configured to provide a low signal when the antifuse is blown.

16. A computer system comprising:

a processor; and

a memory system coupled to the processor and comprising;

a memory controller;

a memory device having a circuit configured to be enabled by a control signal;

an input pin disposed within the memory device and configured to receive the control signal; and

a path selector arranged between the input pin and the circuit and configured to select a signal path to the circuit from the input pin.

17. The memory system of claim 16, wherein the memory device comprises a dynamic random access memory (DRAM) device.

18. The memory system of claim 16, wherein the control signal comprises a chip select signal.

19. The memory system of claim 16, wherein the control signal comprises an inverse chip select signal.

20. The memory system of claim 16, wherein the path selector comprises a fuse controlled path selector.

21. The memory system of claim 20, wherein the fuse controlled path selector includes an antifuse.

22. A method of manufacturing memory, comprising:

providing a plurality of memory die having a fuse controlled path selector within each of the memory die; and

enabling communication paths to circuits within each memory die based on enablement requirements of the circuits.

23. The method of claim 22, comprising stacking the die without providing a redistribution layer.

25. The method of claim 23, comprising stacking each of the plurality of die to form a die stack.

24. (canceled)