Nonvolatile semiconductor memory device

• US 20070153602A1
• Filed: 12/28/2006
• Published: 07/05/2007
• Est. Priority Date: 12/30/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kang, Hee
• Granted Patent: US 7,583,524 B2
• Time in Patent Office: Days
• US Class Current: 365/207
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 51/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
• CPC Class Codes: H10B 51/30 characterised by the memory core region
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Abstract

A nonvolatile semiconductor memory device includes a plurality of 3-dimensional cell arrays to reduce the chip size. The nonvolatile semiconductor memory device includes a unit block cell array including a plurality of vertically multi-layered cell arrays each including a plurality of unit cells arranged in row and column directions, a column address decoder configured to decode a column address to activate a bit line of the selected cell array from the plurality of cell arrays, a sense amplifier unit configured to sense and amplify data of the bit line of the plurality of cell arrays and shared by the unit block cell array, and a vertical address decoding unit configured to decode a vertical address to select one of the plurality of cell arrays and to connect an output signal from the sense amplifier to the bit line of the selected cell array.

Claims

1. A nonvolatile semiconductor memory device comprising:

a unit block cell array including a plurality of vertically layered cell arrays each including a plurality of unit cells arranged in row and column directions;

a column address decoder configured to decode a column address to activate a bit line of a cell array selected from the plurality of cell arrays;

a sense amplifier unit configured to sense and amplify data of the bit line of the plurality of cell arrays and shared by the unit block cell array; and

a vertical address decoding unit configured to decode a vertical address to select one of the plurality of cell arrays and to connect an output signal from the sense amplifier to the bit line of the selected cell array.

2. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of unit bank cell arrays comprising a plurality of unit block cell arrays arranged in directions X, Y, and Z based on a deposition direction of the plurality of cell arrays are configured to perform read/write operations individually.

3. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a row address decoder configured to decode a row address to activate a word line of the selected cell array; and

a row decoding unit configured to selectively connect a word line of the selected cell array to a row line which is output from the row address decoder in response to an output signal from the vertical address decoding unit.

4. The nonvolatile semiconductor memory device according to claim 3, wherein the row address decoder further comprises a row address register configured to output the row address to the row address decoder.

5. The nonvolatile semiconductor memory device according to claim 3, wherein the row address, the column address, and the vertical address are inputted from separate pads.

6. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a column address register configured to output the column address to the column address decoder; and

a vertical address register configured to output the vertical address to the vertical address decoder.

7. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a bank address register configured to output a bank address; and

a bank address decoder configured to decode an output signal from the bank address register so as to select one of the plurality of unit bank cell arrays.

8. The nonvolatile semiconductor memory device according to claim 7, wherein the bank address is inputted from a pad which is separated from pads where the column address and the vertical address are inputted.

9. The nonvolatile semiconductor memory device according to claim 1, wherein the vertical address decoding unit comprises:

a vertical address decoder configured to decode the vertical address to select one of the plurality of cell arrays; and

a sense amplifier decoding unit configured to selectively connect a bit line of the selected cell array to a column line output from the sense amplifier in response to an output signal from the vertical address decoder.

10. The nonvolatile semiconductor memory device according to claim 9, wherein the sense amplifier decoding unit includes a plurality of switches connected between the column line and the bit line and configured to perform a switching operation in response to an output signal from the vertical address decoder.

11. The nonvolatile semiconductor memory device according to claim 1, wherein the sense amplifier unit includes a plurality of sense amplifiers configured to be activated depending on a decoding result of the column address decoder.

12. The nonvolatile semiconductor memory device according to claim 11, wherein one sense amplifier selected from the plurality of sense amplifiers is connected to one bit line in the selected cell array.

13. The nonvolatile semiconductor memory device according to claim 1, wherein the unit cell includes a nonvolatile ferroelectric capacitor.

14. The nonvolatile semiconductor memory device according to claim 1, wherein each of the plurality of cell arrays comprises:

a plurality of bottom word lines;

an insulating layer formed over the plurality of bottom word lines;

a floating channel layer formed over the insulating layer and including a plurality of drain and source regions serially connected to a plurality of channel regions alternately;

a ferroelectric layer formed over the floating channel layer; and

a plurality of word lines formed over the ferroelectric layer so as to be connected to the plurality of bottom word lines,

wherein a different resistance is induced to a channel region of the floating channel layer depending on a polarity state of the ferroelectric layer so that data is read or written.

15. The nonvolatile semiconductor memory device according to claim 14, wherein the plurality of channel regions, the plurality of drain regions, and the plurality of source regions comprise P-type regions.

16. The nonvolatile semiconductor memory device according to claim 14, wherein the plurality of channel regions, the plurality of drain regions, and the plurality of source regions comprise N-type regions.

17. The nonvolatile semiconductor memory device according to claim 14, wherein the floating channel layer comprises a carbon nano-tube.

18. The nonvolatile semiconductor memory device according to claim 14, wherein the floating channel layer comprises silicon.

19. The nonvolatile semiconductor memory device according to claim 14, wherein the floating channel layer comprises germanium.

20. The nonvolatile semiconductor memory device according to claim 14, wherein the floating channel layer comprises an organic semiconductor.