PLL apparatus with power saving mode and method for implementing the same

• US 20070153949A1
• Filed: 12/29/2005
• Published: 07/05/2007
• Est. Priority Date: 12/29/2005
• Status: Abandoned Application

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Hsu, Tse-Hsiang, Chen, Shang-Ping
• Application Number:
  US11/321,921
• Publication Number:
  US 20070153949A1
• Time in Patent Office: Days
• US Class Current: 375/374
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

The invention relates to a PLL apparatus with power saving mode and a method for implementing the same, comprising: a phase detector, a control unit, a charge pump, a loop filter, and a voltage control oscillator. The phase detector generates two detection signals indicating a phase difference between a reference signal and a feedback signal. When the power saving signal is set at a specific logic level, the control unit modifies the two detection signals to be at respective preset levels which keeps the charge pump either charging or discharging an input node of the loop filter to increase/decrease the control voltage outputted by the loop filter. Driven by such a control voltage, the voltage control oscillator generates an oscillating signal at a frequency lower than a normal working frequency so as to achieve power saving objective.

Claims

1. A PLL apparatus with power saving mode, comprising:

a phase comparing unit receiving a reference signal, a feedback signal and a power saving signal, and outputting a phase difference signal at a node based on the reference signal, the feedback signal, and the power saving signal;

a loop filter coupled to the node, generating a control voltage in correspondence with the phase difference signal; and

a voltage control oscillator coupled to the loop filter, generating an oscillating signal based on the control voltage wherein if the power saving signal is set at a first level, the phase comparing unit keeps either charging or discharging the node to make the control voltage generated by the loop filter to drive the voltage control oscillator to output the oscillating signal at a frequency lower than a normal working frequency of the oscillating signal.

2. The PLL apparatus as described in claim 1 wherein the phase comparing unit comprises:

a phase detector receiving the reference and feedback signals and outputting a first and second detection signals indicating a phase difference between the reference and feedback signals;

a control unit connected to the phase detector, receiving the first and second detection signals and the power saving signal, and generating a first and second modified detection signals; and

a charge pump connected between the control unit and the node, receiving the first and second modified detection signals to generate the phase difference signal at the node.

3. The PLL apparatus as described in claim 2 wherein when the power saving signal is set at the first level, the first and second modified detection signals are set at respective preset levels by the control unit so as to keep the charge pump discharging the node to lower the control voltage thereby decreasing a frequency of the oscillating signal.

4. The PLL apparatus as described in claim 2 wherein when the power saving signal is set at the first level, the first and second modified detection signals are set at respective preset levels by the control unit so as to keep the charge pump charging the node to increase the control voltage thereby decreasing a frequency of the oscillating signal.

5. The PLL apparatus as described in claim 2 wherein the control unit comprises:

an inverter for receiving the power saving signal to output an inverted power saving signal;

a first logic gate for receiving the inverted power saving signal and the first detection signal to form the first modified detection signal; and

a second logic gate for receiving the power saving signal and the second detection signal to form the second modified detection signal.

6. The PLL apparatus as described in claim 5 wherein the first logic gate is an AND gate and the second logic gate is an OR gate.

7. The PLL apparatus as described in claim 2 wherein the control unit comprises:

an inverter for receiving the power saving signal to output an inverted power saving signal;

a first logic gate for receiving the power saving signal and the first detection signal to form the first modified detection signal; and

a second logic gate for receiving the inverted power saving signal and the second detection signal to form the second modified detection signal.

8. The PLL apparatus as described in claim 7 wherein the first logic gate is an OR gate and the second logic gate is an AND gate.

9. The PLL apparatus as described in claim 1 wherein the phase comparing unit comprises:

a gating unit receiving the reference signal and the power saving signal, and generating a modified reference signal;

a phase detector receiving the modified reference signal and the feedback signal and outputting a first and second detection signals indicating a phase difference between the modified reference signal and the feedback signal; and

a charge pump connected between the phase detector and the node, receiving the first and second detection signals to generate the phase difference signal at the node, wherein if the power saving signal is set at the first level, the gating unit fixes the modified reference signal at a preset level, otherwise the gating unit makes the modified reference signal equal to the reference signal.

10. The PLL apparatus as described in claim 9 wherein the gating unit is a logic gate.

11. The PLL apparatus as described in claim 1 wherein the phase comparing unit comprises:

a gating unit receiving the feedback signal and the power saving signal and generating a modified feedback signal;

a phase detector receiving the reference signal and the modified feedback signal and outputting a first and second detection signals indicating a phase difference between the reference signal and the modified feedback signal; and

a charge pump connected between the phase detector and the node, receiving the first and second detection signals to generate the phase difference signal at the node, wherein if the power saving signal is set at the first level, the gating unit fixes the modified feedback signal at a preset level, otherwise the gating unit makes the modified feedback signal equal to the feedback signal.

12. The PLL apparatus as described in claim 11 wherein the gating unit is a logic gate.

13. The PLL apparatus as described in claim 1 wherein the oscillating signal is fed back to the phase comparing unit to serve as the feedback signal.

14. The PLL apparatus as described in claim 1, further comprising a frequency divider coupled between the voltage control oscillator and the phase detector for dividing a frequency of the oscillating signal to generate a divided oscillating signal, which is then fed to the phase detector to serve as the feedback signal.

15. A method for implementing power saving of a PLL apparatus, comprising the steps of:

receiving a power saving signal;

keeping either charging or discharging an input node of a loop filter when the power saving signal is set at a first level;

generating a control voltage by means of the loop filter; and

feeding the control voltage to a voltage control oscillator to output an oscillating signal at a frequency lower than a normal working frequency of the oscillating signal.

16. The method as described in claim 15, wherein the step of keeping either charging or discharging the input node of the loop filter comprises:

receiving a reference signal;

generating a first and second detection signals for indicating a phase difference between the reference signal and a feedback signal;

modifying the first and second detection signals in response to the power saving signal to form a first and second modified detection signals; and

charging/discharging the input node of the loop filter by means of a charge pump in accordance with the first and second modified detection signals.

17. The method as described in claim 16, wherein when the power saving signal is set at the first level, the first and second modified detection signals are set at respective preset levels so as to keep discharging the input node of the loop filter to lower the control voltage thereby decreasing a frequency of the oscillating signal.

18. The method as described in claim 16, wherein when the power saving signal is set at the first level, the first and second modified detection signals are set at respective preset levels so as to keep charging the input node of the loop filter to increase the control voltage thereby decreasing a frequency of the oscillating signal.

19. The method as described in claim 16 wherein the step of modifying the first and second detection signals further comprises the steps of:

inverting the power saving signal to generate an inverted power saving signal;

performing a first logic operation on the first detection signal and the inverted power saving signal to form the first modified detection signal; and

performing a second logic operation on the second detection signal and the power saving signal to form the second modified detection signal.

20. The method as described in claim 19 wherein the first logic operation is an AND operation and the second logic operation is an OR operation.

21. The method as described in claim 16 wherein the step of modifying the first and second detection signals comprises the steps of:

inverting the power saving signal to generate an inverted power saving signal;

performing a first logic operation on the first detection signal and the power saving signal to form the first modified detection signal; and

performing a second logic operation on the second detection signal and the inverted power saving signal to form the second modified detection signal.

22. The method as described in claim 21 wherein the first logic operation is an OR operation and the second logic operation is an AND operation.

23. The method as described in claim 16, wherein the oscillating signal serves as the feedback signal.

24. The method as described in claim 16, wherein the feedback signal is generated by dividing a frequency of the oscillating signal.

25. The method as described in claim 15, wherein the step of keeping either charging or discharging the input node of the loop filter comprises:

receiving a reference signal;

modifying a feedback signal in response to the power saving signal to form a modified feedback signal;

generating a first and second detection signals for indicating a phase difference between the reference signal and the modified feedback signal; and

charging/discharging the input node of the loop filter by means of a charge pump in accordance with the first and second detection signals, wherein if the power saving signal is at the first level, the modified feedback signal is fixed at a preset level, otherwise the modified feedback signal equals to the feedback signal.

26. The method as described in claim 25 wherein the modified feedback signal is obtained by performing a logic operation on the power saving signal and the feedback signal.

27. The method as described in claim 25 wherein the oscillating signal serves as the feedback signal.

28. The method as described in claim 25, wherein the feedback signal is generated by dividing a frequency of the oscillating signal.

29. The method as described in claim 15, wherein the step of keeping either charging or discharging the input node of the loop filter comprises:

receiving a reference signal;

modifying the reference signal in response to the power saving signal to form a modified reference signal;

generating a first and second detection signals for indicating a phase difference between the modified reference signal and a feedback signal; and

charging/discharging the input node of the loop filter by means of a charge pump in accordance with the first and second detection signals, wherein if the power saving signal is at the first level, the modified reference signal is fixed at a preset level, otherwise the modified reference signal equals to the reference signal.

30. The method as described in claim 29 wherein the modified reference signal is obtained by performing a logic operation on the power saving signal and the reference signal.

31. The method as described in claim 29 wherein the oscillating signal serves as the feedback signal.

32. The method as described in claim 29, wherein the feedback signal is generated by dividing a frequency of the oscillating signal.