PLL apparatus with power saving mode and method for implementing the same
First Claim
1. A PLL apparatus with power saving mode, comprising:
- a phase comparing unit receiving a reference signal, a feedback signal and a power saving signal, and outputting a phase difference signal at a node based on the reference signal, the feedback signal, and the power saving signal;
a loop filter coupled to the node, generating a control voltage in correspondence with the phase difference signal; and
a voltage control oscillator coupled to the loop filter, generating an oscillating signal based on the control voltage wherein if the power saving signal is set at a first level, the phase comparing unit keeps either charging or discharging the node to make the control voltage generated by the loop filter to drive the voltage control oscillator to output the oscillating signal at a frequency lower than a normal working frequency of the oscillating signal.
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Abstract
The invention relates to a PLL apparatus with power saving mode and a method for implementing the same, comprising: a phase detector, a control unit, a charge pump, a loop filter, and a voltage control oscillator. The phase detector generates two detection signals indicating a phase difference between a reference signal and a feedback signal. When the power saving signal is set at a specific logic level, the control unit modifies the two detection signals to be at respective preset levels which keeps the charge pump either charging or discharging an input node of the loop filter to increase/decrease the control voltage outputted by the loop filter. Driven by such a control voltage, the voltage control oscillator generates an oscillating signal at a frequency lower than a normal working frequency so as to achieve power saving objective.
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Citations
32 Claims
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1. A PLL apparatus with power saving mode, comprising:
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a phase comparing unit receiving a reference signal, a feedback signal and a power saving signal, and outputting a phase difference signal at a node based on the reference signal, the feedback signal, and the power saving signal;
a loop filter coupled to the node, generating a control voltage in correspondence with the phase difference signal; and
a voltage control oscillator coupled to the loop filter, generating an oscillating signal based on the control voltage wherein if the power saving signal is set at a first level, the phase comparing unit keeps either charging or discharging the node to make the control voltage generated by the loop filter to drive the voltage control oscillator to output the oscillating signal at a frequency lower than a normal working frequency of the oscillating signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method for implementing power saving of a PLL apparatus, comprising the steps of:
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receiving a power saving signal;
keeping either charging or discharging an input node of a loop filter when the power saving signal is set at a first level;
generating a control voltage by means of the loop filter; and
feeding the control voltage to a voltage control oscillator to output an oscillating signal at a frequency lower than a normal working frequency of the oscillating signal. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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Specification