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PLL apparatus with power saving mode and method for implementing the same

  • US 20070153949A1
  • Filed: 12/29/2005
  • Published: 07/05/2007
  • Est. Priority Date: 12/29/2005
  • Status: Abandoned Application
First Claim
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1. A PLL apparatus with power saving mode, comprising:

  • a phase comparing unit receiving a reference signal, a feedback signal and a power saving signal, and outputting a phase difference signal at a node based on the reference signal, the feedback signal, and the power saving signal;

    a loop filter coupled to the node, generating a control voltage in correspondence with the phase difference signal; and

    a voltage control oscillator coupled to the loop filter, generating an oscillating signal based on the control voltage wherein if the power saving signal is set at a first level, the phase comparing unit keeps either charging or discharging the node to make the control voltage generated by the loop filter to drive the voltage control oscillator to output the oscillating signal at a frequency lower than a normal working frequency of the oscillating signal.

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