Memory Cell Array

• US 20070155077A1
• Filed: 11/21/2006
• Published: 07/05/2007
• Est. Priority Date: 12/07/2004
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Schloesser, Till
• Granted Patent: US 7,301,799 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

A memory cell array is formed by providing a plurality of memory cells along a substrate, where each of the memory cells includes a storage element and an access transistor. A plurality of bit lines are formed that extend along a first direction of the substrate. A plurality of active area lines and a plurality of isolation trenches are also formed in the semiconductor substrate, with the isolation trenches being adjacent the active area lines such that each isolation trench is disposed between and electrically isolates a first active area line from a second active area line. The access transistors are at least partially formed in the active area lines and electrically couple corresponding storage elements to corresponding bit lines via bit line contacts, and at least a portion of each bit line contact is located at an intersection of a bit line and a corresponding active area line.

Claims

1. A method of forming a memory cell array, the method comprising:

providing a plurality of memory cells along a substrate, each of the memory cells comprising a storage element and an access transistor;

forming a plurality of bit lines that extend along a first direction of the substrate; and

forming a plurality of active area lines and a plurality of isolation trenches in the semiconductor substrate, the isolation trenches being adjacent the active area lines such that each isolation trench is disposed between and electrically isolates a first active area line from a second active area line;

wherein the access transistors are at least partially formed in the active area lines and electrically couple corresponding storage elements to corresponding bit lines via bit line contacts, and at least a portion of each bit line contact is located at an intersection of a bit line and a corresponding active area line.

2. The method of claim 1, wherein each active area line intersects a plurality of bit lines.

3. The method of claim 1, wherein each active area line includes a plurality of bit line contacts such that a first bit line contact of a selected active area line is in contact with a first bit line and a second bit line contact of the at least one active area line is in contact with a second bit line.

4. The method of claim 1, wherein the active area lines are formed as straight lines.

5. The method of claim 1, wherein the active area lines are formed with first portions extending along the first direction of the substrate between neighboring bit lines and second portions extending in a direction transverse the first direction such that the second portions of the active area lines intersect corresponding bit lines.

6. The method of claim 1, wherein each of the storage elements comprises a storage capacitor.

7. The method of claim 6, wherein each storage capacitor comprises a stacked capacitor.

8. The method of claim 1, wherein the active area lines are formed such that an angle between the active area lines and the bit lines is between approximately 10°

to 60°

.

9. The method of claim 1, wherein the active area lines are formed such that an angle between the active area lines and the bit lines is between approximately 10°

to 25°

.

10. The method of claim 1, wherein the active area lines are formed such that an angle between the active area lines and the bit lines is between approximately 18°

to 19°

.

11. The method of claim 1, wherein at least one bit line contact is associated with a first access transistor and a second access transistor that are formed in one active area line.

12. The method of claim 1, further comprising:

forming a plurality of word lines that extend along a second direction of the substrate transverse the first direction, wherein the access transistors are addressed by the word lines.

13. The method of claim 12, further comprising:

forming a plurality of isolation gate lines extending along the second direction of the substrate, wherein each isolation gate line isolates a first transistor from a second transistor.

14. The method of claim 13, wherein the isolation gate lines and the word lines are formed along the substrate such that at least one consecutive arrangement of word lines and isolation gate lines is provided in which a single isolation gate line is disposed between a first set of two word lines and a second set of two word lines.

15. A method of forming bit line contacts in a substrate, the method comprising:

forming a plurality of bit lines that extend along a first direction of the substrate; and

forming a plurality of active area lines in the substrate;

wherein a plurality of bit line contacts are formed along each active area line, and at least a portion of each bit line contact is located at an intersection of a bit line and an active area line.

16. The method of claim 15, wherein a first bit line contact of a selected active area line is in contact with a first bit line and a second bit line contact of the at least one active area line is in contact with a second bit line.

17. The method of claim 15, wherein the active area lines are formed as straight lines.

18. The method of claim 15, wherein the active area lines are formed with first portions extending along the first direction of the substrate between neighboring bit lines and second portions extending in a direction transverse the first direction such that the second portions of the active area lines intersect corresponding bit lines.

19. The method of claim 15, wherein the active area lines are formed such that an angle between the active area lines and the bit lines is between approximately 10°

to 60°

.

20. The method of claim 15, wherein the active area lines are formed such that an angle between the active area lines and the bit lines is between approximately 10°

to 60°

.

21. The method of claim 15, wherein the active area lines are formed such that an angle between the active area lines and the bit lines is between approximately 10°

to 25°

.

22. The method of claim 15, wherein the active area lines are formed such that an angle between the active area lines and the bit lines is between approximately 18°

to 19°

.