GATE STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20070155079A1
• Filed: 12/28/2006
• Published: 07/05/2007
• Est. Priority Date: 12/29/2005
• Status: Abandoned Application

• Current Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Kim, Dae Kyeun
• Application Number:
  US11/617,105
• Publication Number:
  US 20070155079A1
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor gate structure may be manufactured by forming an oxide layer over a silicon substrate before forming a gate insulating layer. The oxide is etched to form an opening that exposes a channel region. After forming a gate insulating layer in the opening, a gate conductor layer is deposited and is etched to form a gate. The oxide layer is etched to leave protective oxide regions at both edges of the gate insulating layer. The oxide regions protect the gate insulating layer from plasma damage during a gate etching process. Also, since the length of the gate insulating layer is smaller than the gate due to the protective oxides, ion diffusion is prevented from causing overlap in low density source and drain regions under the gate insulating layer.

Claims

1. A gate structure of a semiconductor device, comprising:

a gate insulating layer formed over a channel region of a silicon substrate;

protective oxide regions formed at both edges of the gate insulating layer; and

a gate formed over the gate insulating layer and the protective oxide regions.

2. The gate structure of a semiconductor device of claim 1, wherein the length of the gate insulating layer is smaller than the length of the gate.

3. The gate structure of a semiconductor device of claim 1, wherein the length of the gate insulating layer is smaller than the length of the gate by about 100 Å

to 1,000 Å

.

4. The gate structure of a semiconductor device of claim 1, wherein the protective oxide regions are thicker than the gate insulation layer and thinner than the gate.

5. The gate structure of a semiconductor device of claim 1, wherein the thickness of the protective oxide regions is 50 Å

to 500 Å

.

6. The gate structure of a semiconductor device of claim 1, further comprising spacers formed over the side walls of the gate and the protective oxide regions.

7. A method of manufacturing a gate structure of a semiconductor substrate, the method comprising:

forming an oxide layer over a silicon substrate;

etching the oxide layer to form an opening which exposes a channel region of the silicon substrate;

forming a gate insulating layer in the opening over the exposed silicon substrate;

depositing a gate conductor layer to a thickness at least enough to fill the opening; and

etching the gate conductor layer to form a gate and etching the oxide layer to form protective oxide regions at both edges of the gate insulating layer.

8. The method of claim 7, wherein the oxide layer is initially formed using a CVD process.

9. The method of claim 7, wherein the oxide layer is initially formed using a thermal oxidation process.

10. The method of claim 7, wherein, a mask used to etch the opening in the oxide layer is also used to etch the gate conductor layer to form a gate and to etch the oxide layer to form protective oxide regions at both edges of the gate insulating layers.

11. The method of claim 7, wherein the opening in the oxide layer has a length smaller than a length of the etched gate.

12. The method of claim 7, wherein the opening in the oxide layer has a length smaller than a length of the etched gate by about 100 Å

to 1,000 Å

.

13. The method of claim 7, further comprising depositing a spacer insulating layer over the side walls of the gate and over the oxide regions.

14. The method of claim 13, wherein the spacer insulating layer is etched by an anisotropic etching process to form gate spacers.