METHOD OF MANUFACTURING A COPPER INDUCTOR

• US 20070155152A1
• Filed: 12/28/2006
• Published: 07/05/2007
• Est. Priority Date: 12/29/2005
• Status: Abandoned Application

• Current Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Kang, Myung II
• Application Number:
  US11/617,197
• Publication Number:
  US 20070155152A1
• Time in Patent Office: Days
• US Class Current: 438/597
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

An inductor can be integrated with other components in a device formed on one semiconductor chip. The integrated circuit inductor has reduced electric resistance in the conductor and minimized influence on other circuit elements. A method of manufacturing the inductor which minimizes the area occupied by the inductor in a semiconductor chip allows the chip to be located in a small, narrow region along the edge of a chip, with coils which are vertically aligned with respect to the semiconductor substrate.

Claims

1. A method comprising forming a plurality of elements of an inductor by a damascene process.

2. The method of claim 1, wherein the inductor is a copper inductor.

3. The method of claim 1, comprising laminating a first barrier insulating layer and first interlayer dielectric layer over a semiconductor substrate to form a first laminated layer, wherein the first barrier insulating layer and first interlayer dielectric layer are comprised in an element of the inductor.

4. The method of claim 3, comprising:

forming a first trench in the first laminated layer;

applying a first barrier metal layer over the internal wall of the first trench; and

forming a first copper metal layer over the first barrier metal layer to completely fill the first trench to form a first metal interconnection layer.

5. The method of claim 4, comprising:

laminating a second barrier insulating layer and a second interlayer dielectric layer over the first metal interconnection layer to form a second laminated layer;

forming a second trench having a double damascene structure in the second laminated layer; and

applying a second barrier metal layer over the internal wall of the second trench and forming a second copper metal layer over the second barrier metal layer to completely fill the second trench to form a second metal interconnection layer over the first metal interconnection layer.

6. The method of claim 5, comprising:

laminating a third barrier insulating layer and a third interlayer dielectric layer over the second metal interconnection layer to form a third laminated layer;

forming a third trench having a double damascene structure in the third laminated layer; and

applying a third barrier metal layer over the internal wall of the third trench and forming a third copper metal layer over the third barrier metal layer to completely fill the third trench to form a third metal interconnection layer over the second metal interconnection layer.

7. The method of claim 6, wherein the first metal layer and the second metal layer are electrically connected to each other by a via connection included in the double damascene trench structure of the second metal layer.

8. The method of claim 7, wherein the second metal layer and the third metal layer are electrically connected to each other by a via connection included in the double damascene trench structure of the third metal layer.

9. The method of claim 8, wherein the interlayer dielectric layer is formed of a first capping layer, a fluorinated silicate glass (FSG) layer, and a second capping layer.

10. The method of claim 9, wherein:

the first to third metal interconnection layers form rectangular spirals, which are aligned vertically with respect to the semiconductor substrate, and

the end of the first metal interconnection layer and the end of the third metal interconnection layer are terminals of an inductor.

11. The method of claim 9, wherein the barrier insulating layer comprises at least one of SiN and SiC.

12. An apparatus comprising a plurality of elements of an inductor having a damascene structure.

13. The apparatus of claim 12, wherein the inductor is a copper inductor.