Slurry for chemical mechanical polishing process and method of manufacturing semiconductor device using the same

• US 20070155178A1
• Filed: 03/01/2007
• Published: 07/05/2007
• Est. Priority Date: 05/22/2000
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jung-yup, Yoon, Bo-un, Hah, Sang-rok, Kim, Kwang-bok, Kim, Kyung-hyun, Lee, Jong-won, Hong, Chang-ki, Boo, Jae-phill, Park, Young-rae
• Application Number:
  US11/712,931
• Publication Number:
  US 20070155178A1
• Time in Patent Office: Days
• US Class Current: 438/692
• CPC Class Codes: B24B 37/044 characterised by the composition of the lapping agent
• CPC Class Codes: C09G 1/02 containing abrasives or grinding agents abrasives as such C09K3/14; polishing of semi-conductors H01L
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264

Abstract

A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.

Claims

1. A semiconductor device prepared by the sequential steps of:

(a) forming on a semiconductor lower layer a first material layer pattern of a first material which exhibits the property of hydrophobicity with respect to the slurry composition along a surface of said first material;

(b) forming on said surface of said first material and on adjacent surface of said semiconductor lower layer a second material layer of a second material which exhibits the property of hydrophilicity with respect to the slurry composition along a surface of said second material; and

,

(c) performing a chemical mechanical polishing (CMP) process on said surface of said second material using a slurry composition consisting essentially of water, abrasive grains selected from the group consisting of silica (SiO2), alumina (Al2O3), ceria (CeO2), magania (Mn2O3), and mixtures thereof, and about 0.001% to about 5% by weight of a polymer additive selected from the group consisting of poly vinyl methyl ether (PVME), poly ethylene glycol (PEG), poly oxyethylene 23 lauryl ether (POLE), poly propanoic acid (PPA), poly acrylic acid (PAA), poly ether glycol bis ether (PEGBE), and mixtures thereof, wherein the polymer additive improves the selectivity ratio for removal of the silicon oxide layer relative to removal of the polysilicon layer.

2. A semiconductor device prepared in accordance with claim 1 wherein said slurry composition further consists essentially of a surfactant and a pH control agent containing acid or base.

3. A semiconductor device prepared in accordance with claim 1 wherein the pH of the slurry composition is adjusted to within the range of about 7 to 11.

4. A semiconductor device prepared in accordance with claim 1 wherein the concentration of polymer additive ranges from 0.01 % to 1% by weight.

5. A semiconductor device prepared in accordance with claim 1 wherein the selectivity ratio of the slurry composition for removal of the silicon oxide layer relative to removal of the polysilicon layer is a minimum of 1.6.

6. A semiconductor device prepared by the sequential steps of:

(a) forming on a semiconductor substrate an etch mask pattern by depositing on said substrate at least a first material layer of a first material which exhibits the property of hydrophobicity with respect to the slurry composition along a surface of said first material;

(b) forming a trench in the semiconductor substrate to a predetermined depth using said etch mask pattern to guide the trench formation;

(c) forming on the structure where said trench has been formed a second material layer of a second material having the properties of insularity and exhibiting hydrophilicity with respect to the slurry composition along a surface of said second material; and

,

(d) performing a chemical mechanical polishing (CMP) process on said surface of said second material so as to expose said surface of said first material by using a slurry composition consisting essentially of water, abrasive grains selected from the group consisting of silica (SiO2), alumina (Al2O3), ceria (CeO2), magania (Mn2O3), and mixtures thereof, and about 0.001% to about 5% by weight of a polymer additive selected from the group consisting of poly vinyl methyl ether (PVME), poly ethylene glycol (PEG), poly oxyethylene 23 lauryl ether (POLE), poly propanoic acid (PPA), poly acrylic acid (PAA), poly ether glycol bis ether (PEGBE), and mixtures thereof, wherein the polymer additive improves the selectivity ratio for removal of the silicon oxide layer relative to removal of the polysilicon layer.

7. A semiconductor device prepared in accordance with claim 6 wherein the etch mask pattern comprises a stack layer consisting of said first material layer and an anti-reflective layer.

8. A semiconductor device prepared in accordance with claim 6 wherein the method of preparation further comprises the step of forming a first oxide layer between the semiconductor substrate and the first material layer of the etch mask pattern before carrying out step (a).

9. A semiconductor device prepared in accordance with claim 6 wherein the method of preparation further comprises the step of forming a thermal oxide layer on the exposed surface of the trench after carrying out step (b) and before carrying our step (c).

10. A semiconductor device prepared in accordance with claim 6 wherein the method of preparation further comprises the step of removing the remaining first material layer after completing step (d).

11. A semiconductor device prepared in accordance with claim 6 wherein the method of preparation further comprises the step of forming a sacrificial oxide layer on the semiconductor substrate after the step of removing the first material layer.

12. A semiconductor device prepared in accordance with claim 7 wherein said anti-reflective layer is made of silicon oxynitride (SiON).

13. A semiconductor device prepared in accordance with claim 6 wherein the concentration of polymer additive ranges from 0.01% to 1% by weight.

14. A semiconductor device prepared in accordance with claim 6 wherein the selectivity ratio of the slurry composition for removal of the silicon oxide layer relative to removal of the polysilicon layer is a minimum of 1.6.

15. A semiconductor device prepared by the sequential steps of:

(a) forming on an interlayer insulating layer of a semiconductor substrate an upper electrode of a capacitor by depositing on said substrate at least a first material layer of a first material having the properties of conductivity and exhibiting hydrophobicity with respect to the slurry composition along a surface of said first material;

(b) forming on said surface of said first material and on adjacent surface of said semiconductor substrate a second material layer of a second material which exhibits the property of hydrophilicity with respect to the slurry composition along a surface of said second material;

(c) performing a chemical mechanical polishing (CMP) process on said surface of said second material so as to expose said surface of said first material by using a slurry composition consisting essentially of water, abrasive grains selected from the group consisting of silica (SiO2), alumina (Al2O3), ceria (CeO2), magania (Mn2O3), and mixtures thereof, and about 0.001% to about 5% by weight of a polymer additive selected from the group consisting of poly vinyl methyl ether (PVME), poly ethylene glycol (PEG), poly oxyethylene 23 lauryl ether (POLE), poly propanoic acid (PPA), poly acrylic acid (PAA), poly ether glycol bis ether (PEGBE), and mixtures thereof, wherein the polymer additive improves the selectivity ratio for removal of the silicon oxide layer relative to removal of the polysilicon layer; and

,

(d) forming on the resultant structure a third material layer of a third material having the property of insularity.

16. A semiconductor device prepared in accordance with claim 15 wherein said third material exhibits the property of hydrophilicity with respect to the slurry composition along a surface of said third material.

17. A semiconductor device prepared in accordance with claim 15 wherein the method of preparation further comprises the step of performing a CMP process at least one time on said surface of said third material in order to expose said surface of said first material using said slurry composition.

18. A semiconductor device prepared in accordance with claim 15 wherein the method of preparation further comprises the step of reflowing the third material layer under heat after forming said third material layer.

19. A semiconductor device prepared in accordance with claim 15 wherein said first material layer is made of polysilicon and said second material layer is made of silicon oxide.

20. A semiconductor device prepared in accordance with claim 15 wherein a pH control agent containing acid or base is added to the slurry composition to adjust the pH of the slurry composition to within the range of about 7 to 11.

21. A semiconductor device prepared in accordance with claim 15 wherein the concentration of polymer additive ranges from 0.01% to 1% by weight.

22. A semiconductor device prepared in accordance with claim 15 wherein the selectivity ratio of the slurry composition for removal of the silicon oxide layer relative to removal of the polysilicon layer is a minimum of 1.6.