MULTI-STANDARD MULTI-RATE FILTER

• US 20070156800A1
• Filed: 12/15/2006
• Published: 07/05/2007
• Est. Priority Date: 12/16/2005
• Status: Active Grant

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Inventors: Sturza, Mark, Leimer, Donald
• Granted Patent: US 8,176,107 B2
• Time in Patent Office: Days
• US Class Current: 708/300
• CPC Class Codes: H03H 17/0277 comprising recursive filters
• CPC Class Codes: H03H 17/0279 having two phases
• CPC Class Codes: H03H 17/0664 where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation

Abstract

A method is provided for decimating a digital signal by a factor of M and matching it to a desired channel bandwidth. The method applies the digital signal input samples to a (M−1) stage tapped delay line, downsamples the input samples and the output samples of each tapped delay line stage by a factor of M, and applies each of the M downsampled sample value streams to M allpass IRR filters, respectively. The M allpass IRR filtered sample streams are then summed and scaled by a factor of 1/M. The result can then be filtered by a digital channel filter.

Claims

1. A method for decimating a digital signal by a factor of M and matching it to a desired channel bandwidth, comprising:

a. Applying said digital signal input samples to a M−

1 stage tapped delay line;

b. Downsampling said input samples and outputs of said tapped delay line stages by a factor of M;

c. Applying said M downsampled values to M allpass IRR filters where the phase of said allpass IRR filters add constructively at frequencies below a passband frequency, and add destructively at frequencies above a stopband frequency, and where;

i. Said passband frequency is less than the input sample rate divided by 2 times M

ii. Said stopband frequency is greater than the input sample rate divided by 2 times M;

d. Summing the outputs of said M allpass filters;

e. Scaling said sum by a factor of 1/M;

f. Applying said scaled sum to a digital channel filter.

2. The method of claim 1 where said allpass IRR filters are realized as 1-coefficient structures.

3. The method of claim 1 where said allpass IRR filters are realized as 2-coefficient structures.

4. The method of claim 1 where said allpass IRR filters are realized as a cascade of 1-coefficient structures.

5. The method of claim 1 where said allpass IRR filters are designed using differential evolution.

6. The method of claim 1 where said digital channel filter is a generalized N-path polyphase IRR filter.

7. A method for selectively decimating a digital signal by a factor equal to the product of any number of the positive integers M₁, M₂, . . . , and M_n, and matching it to a desired channel bandwidth comprising the steps of:

a. Setting a buffer equal to said digital signal to be decimated;

b. Setting k equal to 1;

c. If said M_k is in said product, inputting said buffer to the input of a M_k-path decimate by M_k method and placing output in said buffer;

d. Incrementing said k;

e. If k less than or equal to n, going to step c;

f. Applying said buffer to a digital channel filter.

8. The method of claim 7 where said M_k-path decimate by M_k methods each comprise the following steps:

a. Applying said buffer input samples to a M_k-1 stage tapped delay line;

b. Downsampling said input sample, and outputs of said tapped delay line stages, by a factor of M_k;

c. Applying said M_k downsampled values to M_k allpass IIR filters each of whose phase responses add constructively at frequencies below a passband frequency, and add destructively at frequencies above a stopband frequency where;

i. Said passband frequency is less than the input sample rate divided by 2 times M_k;

ii. Said stopband frequency is greater than the input sample rate divided by 2 times M_k;

d. Summing the outputs of said M_k allpass filters;

e. Scaling said sum by a factor of 1/M_k.

9. The method of claim 8 where said allpass IRR filters are realized as 1-coefficient structures.

10. The method of claim 8 where said allpass IRR filters are realized as 2-coefficient structures.

11. The method of claim 8 where said allpass IRR filters are realized as a cascade of 1-coefficient structures.

12. The method of claim 8 where said allpass IRR filters are designed using differential evolution.

13. The method of claim 7 where said digital channel filter is a generalized N-path polyphase IRR filter.

14. The method of claim 7 where said decimation ratio is selected based on measured ACI.

15. The method of claim 7 where said decimation ratio is decreased when measured ACI increases.

16. The method of claim 7 where said decimation ratio is increased when measured ACI decreases.

17. A quad rate, multi-standard decimation device with decimation ratio selectable from 2, 3, 4, and 6;

and selectable mode, comprising;

a. A first input switch with one branch for decimate by 3, 4, or 6; and

a second branch for decimate by 2;

b. A first digital filter connected to said first input switch decimate by 3, 4, or 6 branch;

c. A second switch with input connected to said first digital filter output with one branch for decimate by 4 or 6, and a second branch for decimate by 3;

d. A downsample by 2 connected to said second switch decimate by 4 or 6 branch;

e. A first switching mechanism selecting output of said decimate by 2 or decimate by 3 branch of said second switch depending on which path has been selected;

f. A second switching mechanism selecting output of said first switching mechanism or decimate by 2 branch of said first switch depending on which path has been selected;

g. A third switch connected to the output of said second switching mechanism with one branch for decimate by 3 or 6, and a second branch for decimate by 2 or 4;

h. A combined digital filter, decimate by 3 device connected to said third switch decimate by 3 or 6 output;

i. A combined digital filter, decimate by 2 device connected to said third switch decimate by 2 or 4 output;

j. A third switching mechanism selecting output of said combined digital filter, decimate by 3 device or output of said combined digital filter, decimate by 2 device depending on which path has been selected;

k. A second digital filter connected to output of said third switching mechanism;

l. Said second digital filter bandwidth dependent on selected said mode.

18. The device of claim 17 where said modes include DVB-T/H, ISDB-T, and T-DAB.

19. The device of claim 17 where said first digital filter, said second switch, said downsample by 2, and said first switching mechanism comprise:

a. A first switch connected to the input with one branch for decimate by 3 and a second branch for decimate by 4 or 6;

b. A one sample delay connected to the input;

c. A second switch connected to the output of said one sample delay with one branch for decimate by 3 and a second branch for decimate by 4 or 6;

d. A first downsample by 2 connected to said first switch decimate by 4 or 6 branch;

e. A second downsample by 2 connected to said second switch decimate by 4 or 6 branch;

f. A first switching mechanism selecting said first switch decimate by 3 branch or output of said first downsample by 2 depending on which path has been selected;

g. A second switching mechanism selecting said second switch decimate by 3 branch or output of said second downsample by 2 depending on which path has been selected;

h. A first allpass filter connected to the output of said first switching mechanism;

i. A second allpass filter connected to the output of said second switching mechanism;

j. A summation device adding the outputs of said first allpass filter and of said second allpass filter;

k. A scale by ½

device connected to the output of said summation device.

20. The device of claim 17 where said third switch, said combined digital filter, decimate by 3, said combined filter, decimate by 2, and said third switching mechanism comprise:

a. A first switch connected to the input with one branch for decimate by 2 or 4 and a second branch for decimate by 3 or 6;

b. A first one sample delay connected to the input;

c. A second one sample delay connected to the output of said first one sample delay;

d. A second switch connected to the output of said first one sample delay with one branch for decimate by 2 or 4 and a second branch for decimate by 3 or 6;

e. A first downsample by 2 connected to the decimate by 2 or 4 branch of said first switch;

f. A first downsample by 3 connected to the decimate by 3 or 6 branch of the said first switch;

g. A second downsample by 2 connected to the decimate by 2 or 4 branch of said second switch;

h. A second downsample by 3 connected to the decimate by 3 or 6 branch of said second switch;

i. A first switching mechanism selecting output of said first downsample by 2 or output of said first downsample by 3 depending on which path has been selected;

j. A second switching mechanism selecting output of said second downsample by 2 or output of said second downsample by 3 depending on which path has been selected;

k. A third downsample by 3 connected to the output of said second one sample delay;

l. A first allpass filter connected to output of said first switching mechanism;

m. A second allpass filter connected to the output of said second switching mechanism;

n. A third allpass filter connected to the output of said third downsample by 3;

o. A third switching mechanism selecting zero or selecting the output of said third allpass filter depending on the path selected;

p. A summation device adding the outputs of said first allpass filter, said second allpass filter, and said third switching mechanism;

q. A third switch connected to the output of said summation device with one branch for decimate by 2 or 4 and a second branch for decimate by 3 or 6;

r. A scale by ½

connected to the output of the decimate by 2 or 4 branch of said third switch;

s. A scale by ⅓

connected to the output of the decimate by 3 or 6 branch of said third switch;

t. A fourth switching mechanism selecting the outputs of said scale by ½

or said scale by ⅓

depending on the path selected.

21. The device of claim 17 where said second digital filter device comprises:

a. A first allpass filter connected to the input;

b. A second allpass filter connected to the input;

c. A third allpass filter connected to the output of said second allpass filter;

d. A summation device connected to the outputs of said first allpass filter and of said third allpass filter;

e. A scale by ½

device connected to the output of said summation device.

22. The device of claim 17 where said decimation ratio is selected based on measured ACI.

23. The device of claim 17 where said decimation ratio is decreased when measured ACI increases.

24. The device of claim 17 where said decimation ratio is increased when measured ACI decreases.