Method and system for proximity caching in a multiple-core system

• US 20070156963A1
• Filed: 12/30/2005
• Published: 07/05/2007
• Est. Priority Date: 12/30/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chen, Yen-Kuang, Hughes, Christopher
• Granted Patent: US 7,584,327 B2
• Time in Patent Office: Days
• US Class Current: 711/130
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments of the invention relate to a method and system for caching data in a multiple-core system with shared cache. According to the embodiments, data used by the cores may be classified as being of one of predetermined types. The classification may enable efficiencies to be realized by performing different types of handling corresponding to different data types. For example, data classified as likely to be re-used may be stored in a shared cache, in a region of the shared cache that is closest to a core using the data. By storing the data this way, access time and energy consumption may be reduced if the data is subsequently retrieved for use by the core.

Claims

1. A method comprising:

classifying data as being of a first type; and

based on the classification, storing the data in a shared cache of a multiple-core system.

2. The method of claim 1, wherein the data is stored in a region of the shared cache that is closest to a core using the data.

3. The method of claim 1, wherein the classification identifies data that is likely to be re-used.

4. The method of claim 1, wherein the classification identifies data that is likely to be used by one core at a time.

5. The method of claim 1, wherein the classification is based at least in part on software that operates on the data.

6. The method of claim 1, further comprising accessing the data in the shared cache.

7. An article of manufacture tangibly embodying computer-executable instructions for performing a method according to claim 1.

8. A processor comprising:

a plurality of cores;

a shared cache usable by two or more of the cores; and

logic to store data in the shared cache at an address dependent upon a classification of the data.

9. The processor of claim 8, the processor further comprising a pointer to point to a last core to access the data.

10. The processor of claim 8, wherein the classification identifies data that is likely to be re-used.

11. The processor of claim 8, wherein the address corresponds to a region of the shared cache closest to a core using the data.

12. The processor of claim 8, wherein the logic is to store the data at the address after a private cache capacity eviction.

13. The processor of claim 12, the logic to further, after a miss of the data in the private cache, search for the data at the address.

14. The processor of claim 13, the logic to further, if the data is not found at the address, refer to a pointer, the pointer to point to a last core to access the data.

15. A system comprising:

a memory;

a plurality of processors coupled to the memory, at least two of the processors including a plurality of cores;

a shared cache usable by each of the cores; and

logic to store data in the shared cache, in a region of the shared cache that is closest to a core using the data, based on a classification of the data as being of a predetermined type.

16. The system of claim 15, further comprising a pointer to point to a last core to access the data.

17. The system of claim 15, the logic to further, for data needed by a requesting core, determine whether the data is of the predetermined type, and if so, search for the data in the region of the shared cache that is closest to the requesting core.

18. The system of claim 17, the logic to further, if the data is not found in the region of the shared cache that is closest to the requesting core, retrieve the data from one of a private cache of a core previously accessing the data, or a region of the shared cache closest to the core previously accessing the data.

19. The system of claim 15, the logic to further, if data of the predetermined type is missed in a private cache of a requesting core, bring the data into the private cache, and form a pointer to the requesting core.

20. The system of claim 19, the logic to further evict the data from the private cache and store the data in the region of the shared cache that is closest to the requesting core.

21. The system of claim 15, wherein the classification identifies data that is likely to be re-used.

22. An apparatus comprising:

a core;

a private cache associated with the core;

a shared cache; and

logic to store data in the shared cache, in a region of the shared cache that is closest to the core, based on a classification of the data as being one of predetermined types.

23. The apparatus of claim 22, wherein the predetermined types include a first type identifying data as likely to be re-used.

24. The apparatus of claim 22, wherein the predetermined types further include a second type identifying data as unlikely to be re-used;

and the logic to further, based on the classification, store data of the second type in the private cache.

25. The apparatus of claim 22, wherein the predetermined types further include a third type identifying data as likely to be used by more than one core at a time.

26. The apparatus of claim 22, the logic to further, after missing data in the private cache, bring the missed data into the private cache, and form a pointer to point to the core.

27. The apparatus of claim 26, the logic to further evict the missed data from the private cache, and store the evicted data in the region of the shared cache that is closest to the core.

28. The apparatus of claim 24, the logic to further, based on events following an initial classification, reclassify data of the second type as being data of the first type, or vice versa.