Home node aware replacement policy for caches in a multiprocessor system
First Claim
1. A system having comprising:
- a plurality of processor nodes that share distributed memory, each processor node including a processor core;
at least one interconnect interface, each interconnect interface to provide a path from the respective processor node to at least one other processor node of said plurality of processor nodes; and
a cache to store copies of data used by the processor core, the cache to write-back a cache entry selected for eviction from the cache to a memory of the distributed memory from which the cache entry originated, each cache entry to be associated with a t-bit cost metric representing a relative distance between said cache and the originating memory of the cache entry, where t≧
1, said cache to select which cache entry to evict based at least in part on the t-bit cost metric.
2 Assignments
0 Petitions
Accused Products
Abstract
A home node aware replacement policy for a cache chooses to evict lines which belong to local memory over lines which belong to remote memory, reducing the average transaction cost of incorrect cache line replacements. With each entry, the cache stores a t-bit cost metric (t≧1) representing a relative distance between said cache and an originating memory for the respective cache entry. Responsive to determining that no cache entry corresponds to an access request, the replacement policy selects a cache entry for eviction from the cache based at least in part on the t-bit cost metric. The selected cache entry is then evicted from the cache.
-
Citations
20 Claims
-
1. A system having comprising:
a plurality of processor nodes that share distributed memory, each processor node including a processor core;
at least one interconnect interface, each interconnect interface to provide a path from the respective processor node to at least one other processor node of said plurality of processor nodes; and
a cache to store copies of data used by the processor core, the cache to write-back a cache entry selected for eviction from the cache to a memory of the distributed memory from which the cache entry originated, each cache entry to be associated with a t-bit cost metric representing a relative distance between said cache and the originating memory of the cache entry, where t≧
1, said cache to select which cache entry to evict based at least in part on the t-bit cost metric.- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
13. A device comprising:
-
a cost metric encoder, to translate addresses into t-bit cost metrics, where t≧
1 and each t-bit cost metric corresponds a relative latency for completion of at least one data request to a respective address; and
a cache including a plurality of storage locations, each storage location to store data associated with an address together with the t-bit cost metric corresponding to the respective address; and
an interface to receive access requests;
wherein data in a storage location of the plurality of storage locations is to be selected for eviction based at least in part on the t-bit cost metric stored by said storage location, to be replaced by data associated with a requested address, if the cache receives an access request for the requested address and the requested address is not associated with data stored in the cache. - View Dependent Claims (14)
-
-
15. A method comprising:
-
storing, with each entry in a cache, a t-bit cost metric (t≧
1) representing a relative distance between said cache and an originating memory for the respective cache entry;
responsive to determining that no cache entry corresponds to an access request, selecting a cache entry for eviction from the cache based at least in part on the t-bit cost metric; and
evicting the selected cache entry from the cache. - View Dependent Claims (16, 17)
-
-
18. A machine-readable medium storing instructions adapted to implement a cache replacement policy, the cache replacement policy comprising:
-
storing, with each entry in a cache, a t-bit cost metric (t≧
1) representing a relative distance between said cache and an originating memory for the respective cache entry;
responsive to determining that no cache entry corresponds to an access request, selecting a cache entry for eviction from the cache based at least in part on the t-bit cost metric; and
evicting the selected cache entry from the cache. - View Dependent Claims (19, 20)
-
Specification