Processor state restoration and method for resume

• US 20070157045A1
• Filed: 12/30/2005
• Published: 07/05/2007
• Est. Priority Date: 12/30/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rothman, Michael, Zimmer, Vincent, Gu, Xiaogang, Xing, Yuanyuan
• Granted Patent: US 7,793,127 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake

Abstract

In some embodiments, the invention involves efficiently boot and resume a machine from a low power state. In at least one embodiment, the present invention saves the processor state(s) in a buffer that allows fast access upon a resume from sleep mode. When a sleep (S3 mode) is initiated in a platform, processor state context is saved in a system reserved buffer that does not allow access to the operating system. The firmware (EFI) has access to the buffer and upon a resume, the processor context(s) are restored from a fast buffer. Other embodiments are described and claimed.

Claims

1. A system comprising:

at least one processor on a platform;

a chipset coupled to the at least one processor, the chipset to identify when the at least one processor is to be put into a low power state or raised from a low power state to a normal state;

a volatile memory store coupled to the at least one processor to store machine context associated with the at least one processor in a portion of the volatile memory, wherein the portion of volatile memory is reserved for firmware use and inaccessible to an operating system on the platform;

a system management interrupt handler operating on the at least one processor on the platform to save machine context in the volatile memory store, in response to a request to put at least one processor into a low power state, and to restore machine context in response to a request to raise at least one processor from a low power state to a normal state.

2. The system as recited in claim 1, wherein the chipset identifies power management requests via access to one of a pre-defined register and input/output port.

3. The system as recited in claim 1, wherein the volatile memory is system random access memory (RAM).

4. The system as recited in claim 1, wherein the firmware is implemented with an extensible firmware interface (EFI) architecture.

5. The system as recited in claim 1, wherein the reserved portion of volatile memory resides at a location defined by a power management configuration interface.

6. A method comprising:

determining whether a processor is to transition from a higher power state to a lower power state;

if the processor is to transition from a higher power state to a lower power state then;

saving processor context in a volatile memory store coupled to the processor, and

transitioning the processor to the lower power state;

determining when a processor is to transition from a higher power state to a lower power state; and

if the processor is to transition from a lower power state to a higher power state then;

restoring processor context from the volatile memory store, and

transitioning the processor to the higher power state.

7. The method as recited in claim 6, wherein the volatile memory store comprises system random access memory (RAM).

8. The method as recited in claim 7, wherein the processor context is stored in a reserved portion of system RAM, the reserved portion being inaccessible to an operating system running on the processor.

9. The method as recited in claim 6, further comprising:

identifying whether a request has been made to transition the processor to a power state other than a current power state; and

initiating a system management interrupt to handle the request.

10. The method as recited in claim 6, wherein the processor resides on a platform having an extensible firmware interface (EFI) architecture.

11. A machine readable medium having instructions that when executed cause a processor on a platform to:

save processor context in a volatile memory store coupled to the processor in response to a request to transition the processor to a lower power mode;

restore processor context from a volatile memory store coupled to the processor in response to a request to transition the processor to a higher power mode; and

transition the processor to the requested power state.

12. The medium as recited in claim 11, wherein the volatile memory store comprises system random access memory (RAM).

13. The medium as recited in claim 12, wherein the processor context is stored in a reserved portion of system RAM, the reserved portion being inaccessible to an operating system running on the processor.

14. The medium as recited in claim 11, further comprising instructions that when executed cause the processor to:

identify whether a request has been made to transition the processor to a power state other than a current power state; and

initiate a system management interrupt to handle the request.

15. The medium as recited in claim 11, wherein the platform comprises an extensible firmware interface (EFI) architecture.