Techniques to perform forward error correction for an electrical backplane

• US 20070157060A1
• Filed: 01/04/2006
• Published: 07/05/2007
• Est. Priority Date: 01/04/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ovchinnikov, Andrei, Chang, Luke, Belogolovy, Andrey, Ganga, Ilango
• Granted Patent: US 7,676,733 B2
• Time in Patent Office: Days
• US Class Current: 714/752
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: H03M 13/33 Synchronisation based on error coding or decoding
• CPC Class Codes: H03M 13/63 Joint error correction and other techniques H03M13/31 and H03M13/33 take precedence
• CPC Class Codes: H03M 13/6312 Error control coding in combination with data compression
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0042 Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape H04L1/0067 takes precedence
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0047 Decoding adapted to other signal detection operation in conjunction with sequence estimation or equalization H04L25/03286
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0058 Block-coded modulation
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal
• CPC Class Codes: Y02D 30/00 Reducing energy consumption in communication networks

Abstract

Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. Other embodiments are described and claimed.

Claims

1. An apparatus comprising a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

2. The apparatus of claim 1, comprising a forward error correction encoder to encode a physical coding sublayer block of information by compressing said two bit synchronization header with said single bit.

3. The apparatus of claim 1, comprising a forward error correction encoder to comprise:

a reverse gearbox;

a compressor to couple to said reverse gearbox;

a selector to couple to said compressor;

a parity generator to couple to said compressor;

a multiplexer to couple to said compressor, selector and said parity generator;

a scrambler to couple to said multiplexer; and

a pseudo-noise generator to couple to said scrambler.

4. The apparatus of claim 1, comprising a forward error correction decoder and block synchronizer to decode a physical coding sublayer block of information by reconstructing said two bit synchronization header using said single bit.

5. The apparatus of claim 1, comprising a forward error correction decoder and block synchronizer to comprise:

a descrambler;

a pseudo-noise generator to couple to said descrambler;

a synchronizer to couple to said descrambler;

a decoder to couple to said synchronizer;

an error monitor to couple to said decoder; and

a reconstructor to couple to said decoder.

6. A system, comprising:

a communications medium;

a connector to couple to said communications medium; and

a network interface to couple to said connector, said network interface having a physical layer unit with a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

7. The system of claim 6, comprising a forward error correction encoder to encode a physical coding sublayer block of information by compressing said two bit synchronization header with said single bit.

8. The system of claim 6, comprising a forward error correction encoder to comprise:

a reverse gearbox;

a compressor to couple to said reverse gearbox;

a selector to couple to said compressor;

a parity generator to couple to said compressor;

a multiplexer to couple to said compressor, selector and said parity generator;

a scrambler to couple to said multiplexer; and

a pseudo-noise generator to couple to said scrambler.

9. The system of claim 6, comprising a forward error correction decoder and block synchronizer to decode a physical coding sublayer block of information by reconstructing said two bit synchronization header using said single bit.

10. The system of claim 6, comprising a forward error correction decoder and block synchronizer to comprise:

a descrambler;

a pseudo-noise generator to couple to said descrambler;

a synchronizer to couple to said descrambler;

a decoder to couple to said synchronizer;

an error monitor to couple to said decoder; and

a reconstructor to couple to said decoder.

11. A method comprising performing forward error correction using a single bit to represent a two bit synchronization header.

12. The method of claim 11, comprising encoding a physical coding sublayer block of information by replacing said two bit synchronization header with said single bit.

13. The method of claim 11, comprising:

receiving physical coding sublayer blocks of information;

compressing two synchronization bits from each block to a single bit;

generating parity check bits for said blocks; and

generating a forward error correction frame using said blocks and said parity check bits.

14. The method of claim 11, comprising decoding a physical medium attachment sublayer block of information by reconstructing said two bit synchronization header using said single bit.

15. The method of claim 11, comprising receiving physical coding sublayer blocks of information;

decoding each physical coding sublayer block;

retrieving parity check bits for said physical coding sublayer blocks; and

performing forward error correction using said parity check bits.

16. An article comprising a machine-readable storage medium containing instructions that if executed enable a system to perform forward error correction using a single bit to represent a two bit synchronization header.

17. The article of claim 16, further comprising instructions that if executed enable the system to encode a physical coding sublayer block of information by compressing said two bit synchronization header with said single bit.

18. The article of claim 16, further comprising instructions that if executed enable the system to receive physical coding sublayer blocks of information, compress two synchronization bits from each block with a single bit, generate parity check bits for said blocks, and generate a forward error correction frame using said blocks and said parity check bits.

19. The article of claim 16, further comprising instructions that if executed enable the system to decode a physical coding sublayer block of information by reconstructing said two bit synchronization header using said single bit.

20. The article of claim 16, further comprising instructions that if executed enable the system to receive physical coding sublayer blocks of information, decode each physical coding sublayer block, retrieve parity check bits for said physical coding sublayer blocks, and perform forward error correction using said parity check bits.