Techniques for reducing error propagation using modulation codes having a variable span

• US 20070157067A1
• Filed: 01/04/2006
• Published: 07/05/2007
• Est. Priority Date: 01/04/2006
• Status: Active Grant

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Hitachi Global Storage Technologies Netherlands BV (Western Digital Corporation)
• Inventors: Blaum, Mario, Lakovic, Ksenija
• Granted Patent: US 7,696,908 B2
• Time in Patent Office: Days
• US Class Current: 714/784
• CPC Class Codes: G11B 20/10175 PR4, PR(1,0,-1), i.e. partial response class 4, polynomial (1+D)(1-D)=(1-D2)
• CPC Class Codes: G11B 20/1426 conversion to or from block codes or representations thereof
• CPC Class Codes: G11B 2220/2516 Hard disks
• CPC Class Codes: H03M 13/53 Codes using Fibonacci numbers series
• CPC Class Codes: H03M 5/145 Conversion to or from block codes or representations thereof

Abstract

Techniques are provided for reducing error propagation in encoded data using Fibonacci modulation codes. The Fibonacci modulation codes have a Fibonacci base with a variable span that limits error propagation. Some of the elements in the Fibonacci base have a larger span than limited span elements in the base. Errors occurring in bit positions of an encoded sequence that correspond to the limited span elements do not propagate to adjacent bytes in the decoded sequence. The Fibonacci modulation codes can also have a relatively high code rate.

Claims

1. A system for imposing modulation constraints on input sequences to remove a subset of the input sequences, the system comprising:

a modulation encoder that encodes input sequences to generate encoded sequences using a Fibonacci base having a variable span; and

a modulation decoder that decodes the encoded sequences using the Fibonacci base to generate decoded sequences.

2. The system defined in claim 1 wherein a subset of elements in the base have a limited span that prevents errors occurring in a corresponding subset of bit positions in the encoded sequences from propagating to adjacent bytes in the decoded sequence.

3. The system defined in claim 1 wherein the modulation encoder is preceded by a Reed-Solomon encoder.

4. The system defined in claim 3 wherein the Reed-Solomon byte size is equal to 10.

5. The system defined in claim 3 wherein the Reed-Solomon byte size is equal to 12.

6. The system defined in claim 4 wherein the modulation encoder generates a code rate of 10k/(10k+1), where k is a positive integer k=1,2 . . . .

7. The system defined in claim 5 wherein the modulation encoder generates a code rate of 12k/(12k+1), where k is a positive integer k=1,2 . . . .

8. The system defined in claim 1 wherein the modulation encoder generates a code rate of 24/25.

9. The system defined in claim 1 wherein the modulation encoder generates a code rate of 36/37.

10. The system defined in claim 1 wherein the modulation encoder and modulation decoder are implemented by a controller in a hard disk drive.

11. The system defined in claim 1 wherein the modulation encoder and modulation decoder are implemented by a controller for a data communication system.

12. A method for imposing modulation constraints on input sequences to remove a set of forbidden input sequences, the method comprising:

encoding the input sequences with a modulation encoder to generate encoded sequences using a Fibonacci base with a variable span; and

decoding the encoded sequences with a modulation decoder to generate decoded sequences using the Fibonacci base, wherein a subset of elements in the base have a limited span that prevents errors occurring in a corresponding subset of bit positions in the encoded sequences from propagating to adjacent bytes in the decoded sequences.

13. The method defined in claim 12 further comprising:

encoding a bit stream using a Reed-Solomon code to generate the input sequences before being provided to the modulation encoder.

14. The method defined in claim 12 wherein encoding the input sequences using the modulation encoder to generate the encoded sequences further comprises encoding the input sequences using the modulation encoder to provide a code rate of 10k/(10k+1), where k is a positive integer k=1,2 . . . .

15. The method defined in claim 12 wherein encoding the input sequences using the modulation encoder to generate the encoded sequences further comprises encoding the input sequences using the modulation encoder to provide a code rate of 12k/(12k+1), where k is a positive integer k=1,2 . . . .

16. The method defined in claim 12 wherein encoding the input sequences and decoding the encoded sequences are performed by a chipset in a hard disk drive system.

17. A controller for imposing modulation constraints on input sequences, the controller comprising:

a modulation encoder that encodes input sequences to generate encoded sequences using a Fibonacci base having a variable span; and

a modulation decoder that decodes the encoded sequences using the Fibonacci base to generate decoded sequences, wherein a subset of elements in the Fibonacci base have a limited span that prevents errors occurring in bit positions of the encoded sequences that correspond to the subset of elements from propagating to adjacent bytes in the decoded sequences.

18. The controller defined in claim 17 wherein the controller is part of a hard disk drive system.

19. The controller defined in claim 17 wherein the modulation encoder is preceded by a Reed-Solomon encoder.

20. The controller defined in claim 17 wherein the modulation encoder and modulation decoder are implemented for a data communication system.