Yield-limiting design-rules-compliant pattern library generation and layout inspection

• US 20070157153A1
• Filed: 12/30/2005
• Published: 07/05/2007
• Est. Priority Date: 12/30/2005
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Eib, Nicolas, Croffie, Ebo
• Granted Patent: US 7,458,060 B2
• Time in Patent Office: Days
• US Class Current: 716/52
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method and system is provided for analyzing process window compliance of an integrated circuit design. Aspects of the present invention include identifying layout pattern configurations that have process windows that fail to meet respective local performance specifications; searching for any layout pattern configurations in a design that substantially match any of the identified layout pattern configurations; and modifying any matching layout pattern configurations found in the design to make the layout pattern configurations compliant with their respective process windows.

Claims

1. A computer-implemented method for analyzing process window compliance of a design, comprising:

identifying layout pattern configurations that have process windows that fail to meet respective local performance specifications;

searching for any layout pattern configurations in the design that substantially match any of the identified layout pattern configurations; and

modifying any matching layout pattern configurations found in the design to make the layout pattern configurations compliant with their respective process windows.

2. The method of claim 1 further comprising storing the identified pattern configurations in a yield-limiting pattern database.

3. The method of claim 1 wherein searching for the layout pattern configurations in the design further comprises performing process window simulation on the matching layout pattern configurations found in the design to verify that the layout patterns are yield-limiting.

4. The method of claim 1 wherein identifying layout pattern configurations further comprises:

generating design-rule-compliant pattern configurations using design rules;

performing optical proximity correction (OPC) on the design-rule-compliant pattern configurations to create a set of one more OPCed pattern configurations;

performing process window simulations on the set of OPCed pattern configurations; and

analyzing the process window simulations for the OPCed patterns, and identifying any yield-limiting pattern configurations.

5. The method of claim 4 wherein the layout pattern configurations comprise at least one of random logic pattern configurations and SRAM pattern configurations.

6. The method of claim 4 wherein generating the layout pattern configurations further comprises:

given as input at least one of an synthetic layout pattern and real layout pattern, identifying minimum feature size, minimum spacing, maximum feature size, and maximum spacing for each layer defined by process design rules for the layout pattern;

designing an initial set of layout pattern configurations from the input pattern;

varying the feature sizes and spacing between the features in the initial set of layout pattern configurations within the design rules to create design-rule-compliant modified feature patterns; and

generating the layout pattern configurations by arranging combinations are the modified feature patterns.

7. The method of claim 4 wherein performing process window simulations on the set of OPCed pattern configurations further comprises:

calibrating a process simulation tool with data from a mask lithography process that will be used to generate the pattern configurations;

performing the process window simulations with mask error specifications for the OPCed pattern configurations to emulate the mask and lithography process; and

building a yield-limiting pattern configuration using features that are not process window compliant.

8. An executable software product stored on a computer-readable medium containing program instructions for analyzing process window compliance of a design, the program instructions for:

identifying layout pattern configurations that have process windows that fail to meet respective local performance specifications;

searching for any layout pattern configurations in the design that substantially match any of the identified layout pattern configurations; and

modifying any matching layout pattern configurations found in the design to make the layout pattern configurations compliant with their respective process windows.

9. The software product of claim 8 further comprising storing the identified pattern configurations in a yield-limiting pattern database.

10. The software product of claim 8 wherein searching for the layout pattern configurations in the design further comprises performing process window simulation on the matching layout pattern configurations found in the design to verify that the layout patterns are yield-limiting.

11. The software product of claim 8 wherein identifying layout pattern configurations further comprises:

generating design-rule-compliant pattern configurations using design rules;

performing optical proximity correction (OPC) on the design-rule-compliant pattern configurations to create a set of one more OPCed pattern configurations;

performing process window simulations on the set of OPCed pattern configurations; and

analyzing the process window simulations for the OPCed patterns, and identifying any yield-limiting pattern configurations.

12. The software product of claim 11 wherein the layout pattern configurations comprise at least one of random logic pattern configurations and SRAM pattern configurations.

13. The software product of claim 11 wherein generating the layout pattern configurations further comprises:

given as input at least one of an synthetic layout pattern and real layout pattern, identifying minimum feature size, minimum spacing, maximum feature size, and maximum spacing for each layer defined by process design rules for the layout pattern;

designing an initial set of layout pattern configurations from the input pattern;

varying the feature sizes and spacing between the features in the initial set of layout pattern configurations within the design rules to create design-rule-compliant modified feature patterns; and

generating the layout pattern configurations by arranging combinations are the modified feature patterns.

14. The software product of claim 11 wherein performing process window simulations on the set of OPCed pattern configurations further comprises:

calibrating a process simulation tool with data from a mask lithography process that will be used to generate the pattern configurations;

performing the process window simulations with mask error specifications for the OPCed pattern configurations to emulate the mask and lithography process; and

building a yield-limiting pattern configuration using features that are not process window compliant.

15. A system for analyzing process window compliance of a design, comprising:

a memory for storing layout pattern configurations, design data for a design, and local performance specifications; and

a processor coupled to the memory for executing a process compliance window application, the process compliance window application functional for,

identifying the layout pattern configurations that have process windows that fail to meet respective local performance specifications;

searching for any layout pattern configurations in the design data that substantially match any of the identified layout pattern configurations; and

modifying any matching layout pattern configurations found in the design data to make the layout pattern configurations compliant with their respective process windows.