SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

• US 20070158736A1
• Filed: 12/27/2006
• Published: 07/12/2007
• Est. Priority Date: 12/28/2005
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Arai, Fumitaka, Shirota, Riichiro, Mizukami, Makoto
• Granted Patent: US 7,696,559 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained, pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.

Claims

1. A semiconductor memory device comprising:

a semiconductor substrate;

an impurity diffusion layer formed in a cell array area of the semiconductor substrate to serve as a common source line in the cell array;

a gate wiring stack body formed on the cell array area of the substrate with an elongate pattern, in which multiple gate wirings are stacked and separated from each other with insulating films interposed therebetween;

a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained;

a plurality of pillar-shaped semiconductor layers arranged in the elongated direction of the gate wiring stack body at a certain pitch, at least one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, other side surfaces thereof being in contact with a device isolating dielectric film, each the pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer and a lower impurity concentration than the impurity diffusion layer; and

data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.

2. The semiconductor memory device according to claim 1, wherein

the gate wiring stack body and one of the pillar-shaped semiconductor layers opposed to it via the gate insulating film constitute a NAND cell unit. which includes vertical select gate transistors formed at the lowest portion and the uppermost portion of the pillar-shaped semiconductor layer with the gate wirings serving as select gate lines and vertical memory cells stacked between the vertical select gate transistors with the gate wirings serving as word lines.

3. The semiconductor memory device according to claim 2, wherein

one side surface of each pillar-shaped semiconductor layer Is opposed to the gate wiring stack body while the remaining three side surfaces thereof are in contact with a device insulating film.

4. The semiconductor memory device according to claim 3 wherein

a plurality of the gate wiring stack bodies are arranged, and

the pillar-shaped semiconductor layers are arranged along the same side surfaces of the respective gate wiring stack bodies.

5. The semiconductor memory device according to claim 3, wherein

a plurality of the gate wiring stack bodies are arranged, and

the pillar-shaped semiconductor layers are arranged in such a manner that one array is opposed to one side surface of one gate wiring stack body;

and the following array to the other side surface of the following gate wiring stack body.

6. The semiconductor memory device according to claim 2, wherein

a plurality of the gate wiring stack bodies are arranged, and

opposite side surfaces of one of the pillar-shaped semiconductor layers are opposed to adjacent two gate wiring stack bodies via the gate insulating films, respectively;

and the remaining two side surfaces are in contact with the device isolating film, and

first and second NAND cell units are formed to share the one of the pillar-shaped semiconductor layers as channel bodies thereof and share one of the data lines.

7. The semiconductor memory device according to claim 6, wherein

in a data read mode, one of the first and second NAND cell units is selected while all memory cells in the other are so biased as to be off without regard to cell data.

8. The semiconductor memory device according to claim 2, wherein

a plurality of the gate wiring stack bodies are arranged, and

two arrays of the pillar-shaped semiconductor layers are disposed along each gate wiring stack body so as to be opposed to opposite side surfaces of the gate wiring stack body via gate insulating films.

9. The semiconductor memory device according to claim 8, wherein

two pillar-shaped semiconductor layers sandwiching one of the gate wiring stack bodies are coupled to a common data line.

10. The semiconductor memory device according to claim 8, wherein

two pillar-shaped semiconductor layers sandwiching one of the gate wiring stack bodies are coupled to different data lines from each other.

11. The semiconductor memory device according to claim 2, wherein

a plurality of the gate wiring stack bodies are arranged, and

adjacent two arrays of the pillar-shaped semiconductor layers are opposed to opposite side surfaces of each gate wiring stack body via the gate insulating films, while adjacent two gate wiring stack bodies are opposed to opposite side surfaces of each array of the pillar-shaped semiconductor layers.

12. The semiconductor memory device according to claim 11, wherein

two pillar-shaped semiconductor layers sandwiching one of the gate wiring stack bodies are coupled to a common data line.

13. The semiconductor memory device according to claim 11, wherein

two pillar-shaped semiconductor layers sandwiching one of the gate wiring stack bodies are coupled to different data lines from each other.

14. The semiconductor memory device according to claim 2, wherein

at least one of the vertical select gate transistors in the NAND cell unit has a gate insulating film with no charge storage layer formed therein.

15. The semiconductor memory device according to claim 1, wherein

the gate wirings in the gate wiring stack body are formed of metal films or metal silicide films.

16. A method of fabricating a semiconductor memory device comprising:

forming a plurality of polycrystalline silicon films, which are stacked and separated from each other with insulating films interposed therebetween, in a cell array formation area of a semiconductor substrate;

etching the stack structure of the polycrystalline silicon films and the insulating films to form a gate wiring stack body with an elongate pattern, in which a plurality of gate wirings are stacked via the insulating films;

forming a gate insulating film on a first side surface of the gate wiring stack body, in which an insulating charge storage layer is formed,

forming a plurality of pillar-shaped semiconductor layers with the same conductivity type as the impurity diffusion layer and a lower impurity concentration than the impurity diffusion layer, which are arranged in the elongated direction of the gate wiring stack body and opposed to the first side surface of the gate wiring stack body via the gate insulating film;

forming a metal film on the second side surface of the gate wiring stack body, and annealing it to make the gate wirings silicides; and

forming data lines to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.

17. The method according to claim 16, wherein

the procedure of forming the gate insulating film comprises:

sequentially depositing a first silicon oxide film a silicon nitride film serving as the charge storage layer and a second silicon oxide film or another insulator film with a dielectric coefficient higher than the silicon oxide to form the gate insulating film; and

removing the gate insulating film except that disposed on the first side surface of the gate wiring stack body.

18. The method according to claim 16, wherein

the procedure of forming the pillar-shaped semiconductor layers comprises;

forming a semiconductor layer on the semiconductor substrate, on which the gate wiring stack body is formed with the gate insulating film formed on the first side surface of the gate wiring stack body;

annealing the semiconductor layer to crystallize it; and

patterning the semiconductor layer to divide it into a plurality of the pillar-shaped semiconductor layers.