Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement

• US 20070158756A1
• Filed: 01/04/2007
• Published: 07/12/2007
• Est. Priority Date: 01/12/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Dreeskornfeld, Lars, Specht, Michael, Hofmann, Franz, Luyken, Johannes
• Granted Patent: US 7,692,246 B2
• Time in Patent Office: Days
• US Class Current: 257/374
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

The present invention provides a production method for a FinFET transistor arrangement, and a corresponding FinFET transistor arrangement. The method comprises the following steps: provision of a substrate (106, 108); formation of an active region (1) on the substrate, said active region having a source region (114), a drain region (116) and an intervening fin-like channel region (113b′; 113b″) for each individual FinFET transistor; formation of a gate dielectric (11) and a gate region (13, 14, 15) over the fin-like channel region (113b′; 113b″) for each individual FinFET transistor; the formation of the fin-like channel region (113b′; 113b″) having the following steps: formation of a hard mask (S1-S4) on the active region (1), said hard mask having a pad oxide layer (30), an overlying pad nitride layer (50) and nitride sidewall spacers (7); anisotropic etching of the active layer (1) using the hard mask (S1-S4) for the formation of STI trenches (G1-G5); filling of the STI trenches (G1-G5) with an STI oxide filling (9); polishing-back of the STI oxide filling (9) as far as the top side of the hard mask (S1-S4); etching-back of the polished-back STI oxide filling (9) as far as a residual height (h′) in the STI trenches (G1-G5); selective removal of the pad nitride layer (50) and the nitride sidewall spacers (7) with respect to the pad oxide layer (30), the etched-back STI oxide filling (9) and the active region (1) for the formation of a modified hard mask (S1′-S4′); anisotropic etching of the active layer (1) using the modified hard mask (S1′-S4′) for the formation of widened STI trenches (G1′-G5′), the fin-like channel regions (113b′; 113b″) of the active region (1) remaining for each individual FinFET transistor.

Claims

1. Production method for a FinFET transistor arrangement comprising the following steps:

provision of a substrate (106, 108);

formation of an active region (1) on the substrate, said active region having a source region (114), a drain region (116) and an intervening fin-like channel region (113b′

;

113b″

) for each individual FinFET transistor;

formation of a gate dielectric (11) and a gate region (13, 14, 15) over the fin-like channel region (113b′

;

113b″

) for each individual FinFET transistor;

the formation of the fin-like channel region (113b′

;

113b″

) having the following steps;

formation of a hard mask (S1-S4) on the active region (1), said hard mask having a pad oxide layer (30), an overlying pad nitride layer (50) and nitride sidewall spacers (7);

anisotropic etching of the active layer (1) using the hard mask (S1-S4) for the formation of STI trenches (G1-G5);

filling of the STI trenches (G1-G5) with an STI oxide filling (9);

polishing-back of the STI oxide filling (9) as far as the top side of the hard mask (S1-S4);

etching-back of the polished-back STI oxide filling (9) as far as a residual height (h′

) in the STI trenches (G1-G5);

selective removal of the pad nitride layer (50) and the nitride sidewall spacers (7) with respect to the pad oxide layer (30), the etched-back STI oxide filling (9) and the active region (1) for the formation of a modified hard mask (S1′

-S4′

);

anisotropic etching of the active layer (1) using the modified hard mask (S1′

-S4′

) for the formation of widened STI trenches (G1′

-G5′

), the fin-like channel regions (113b′

;

113b″

) of the active region (1) remaining for each individual FinFET transistor.

2. Production method according to claim 1, characterized in that the anisotropic etching of the active layer (1) using the modified hard mask (S1′

-S4′

) is effected as far as the residual height (h′

) of the etched-back STI oxide filling (9).

3. Production method according to claim 1, characterized in that the anisotropic etching of the active layer (1) using the modified hard mask (S1′

-S4′

) is effected as far as below the residual height (h′

) of the etched-back STI oxide filling (9), with the result that a respective gap region (u1-u5) arises between the fin-like channel region (113b″

) and the etched-back STI oxide filling (9), and in that the respective gap region (u1-u5) is filled with an insulation layer (17) prior to the formation of the gate dielectric (11) and the gate region (13, 14, 15).

4. Production method according to claim 3, characterized in that the filling of the respective gap region (u1-u5) is effected by deposition and anisotropic etching-back of an oxide layer (17) with a thickness of approximately half the width of the gap regions (u1-u5).

5. Production method according to one of the preceding claims, characterized in that the modified hard mask (S1′

-S5′

) is removed prior to the formation of the gate dielectric (11) and the gate region (13, 14, 15) over the fin-like channel region (113b′

;

113b″

)

6. Production method according to one of the preceding claims, characterized in that the following steps are carried out for the formation of the gate dielectric (11) and the gate region (13, 14, 15) over the fin-like channel region (113b′

;

113b″

);

deposition of the gate dielectric (11);

deposition of a TaN layer (13) over the gate dielectric (11); and

filling of the modified STI trenches (G1′

-G5′

) with a polysilicon filling (14).

7. Production method according to claim 6, characterized in that the polysilicon filling (14) is planarized and a metal silicide layer (15) is deposited over it.

8. FinFET transistor arrangement comprising:

a substrate (106, 108);

an active region (1) on the substrate, said active region having a source region (114), a drain region (116) and an intervening fin-like channel region (113b′

;

113b″

) for each individual FinFET transistor;

a gate dielectric (11) and a gate region (13, 14, 15) over the fin-like channel region (113b′

;

113b″

) for each individual FinFET transistor;

a respective region with an STI oxide filling (9), over which region the gate dielectric (11) and the gate region (13, 14, 15) run, being provided between adjacent fin-like channel regions (113b′

;

113b″

) in the active region (1).

10. FinFET transistor arrangement according to claim 8, characterized in that the STI oxide filling (9) reaches as far as above the underside of the fin-like channel. regions (113b′

;

113b″

) and a gap region (u1-u5) filled with an insulating filling (17) is provided between the respective fin-like channel region (113b″

) and the STI oxide filling (9).

9. FinFET transistor arrangement according to llaim 8, characterized in that the STI oxide filling (9) reaches as far as the underside of the fin-like channel regions (113b′

;

113b″

).